Lines Matching +full:way +full:- +full:select
1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND
7 select ARCH_HAS_BINFMT_FLAT
8 select ARCH_HAS_CACHE_LINE_SIZE if OF
9 select ARCH_HAS_CPU_CACHE_ALIASING
10 select ARCH_HAS_CPU_FINALIZE_INIT if MMU
11 select ARCH_HAS_CRC32 if KERNEL_MODE_NEON
12 select ARCH_HAS_CRC_T10DIF if KERNEL_MODE_NEON
13 select ARCH_HAS_CURRENT_STACK_POINTER
14 select ARCH_HAS_DEBUG_VIRTUAL if MMU
15 select ARCH_HAS_DMA_ALLOC if MMU
16 select ARCH_HAS_DMA_OPS
17 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
18 select ARCH_HAS_ELF_RANDOMIZE
19 select ARCH_HAS_FORTIFY_SOURCE
20 select ARCH_HAS_KEEPINITRD
21 select ARCH_HAS_KCOV
22 select ARCH_HAS_MEMBARRIER_SYNC_CORE
23 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
24 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
25 select ARCH_HAS_SETUP_DMA_OPS
26 select ARCH_HAS_SET_MEMORY
27 select ARCH_STACKWALK
28 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
29 select ARCH_HAS_STRICT_MODULE_RWX if MMU
30 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
31 select ARCH_HAS_SYNC_DMA_FOR_CPU
32 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
33 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
34 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
35 select ARCH_HAS_GCOV_PROFILE_ALL
36 select ARCH_KEEP_MEMBLOCK
37 select ARCH_HAS_UBSAN
38 select ARCH_MIGHT_HAVE_PC_PARPORT
39 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
40 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
41 select ARCH_NEED_CMPXCHG_1_EMU if CPU_V6
42 select ARCH_SUPPORTS_ATOMIC_RMW
43 select ARCH_SUPPORTS_CFI_CLANG
44 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
45 select ARCH_SUPPORTS_PER_VMA_LOCK
46 select ARCH_USE_BUILTIN_BSWAP
47 select ARCH_USE_CMPXCHG_LOCKREF
48 select ARCH_USE_MEMTEST
49 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
50 select ARCH_WANT_GENERAL_HUGETLB
51 select ARCH_WANT_IPC_PARSE_VERSION
52 select ARCH_WANT_LD_ORPHAN_WARN
53 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
54 select BUILDTIME_TABLE_SORT if MMU
55 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE)
56 select CLONE_BACKWARDS
57 select CPU_PM if SUSPEND || CPU_IDLE
58 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
59 select DMA_DECLARE_COHERENT
60 select DMA_GLOBAL_POOL if !MMU
61 select DMA_NONCOHERENT_MMAP if MMU
62 select EDAC_SUPPORT
63 select EDAC_ATOMIC_SCRUB
64 select GENERIC_ALLOCATOR
65 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
66 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
67 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
68 select GENERIC_IRQ_IPI if SMP
69 select GENERIC_CPU_AUTOPROBE
70 select GENERIC_CPU_DEVICES
71 select GENERIC_EARLY_IOREMAP
72 select GENERIC_IDLE_POLL_SETUP
73 select GENERIC_IRQ_MULTI_HANDLER
74 select GENERIC_IRQ_PROBE
75 select GENERIC_IRQ_SHOW
76 select GENERIC_IRQ_SHOW_LEVEL
77 select GENERIC_LIB_DEVMEM_IS_ALLOWED
78 select GENERIC_PCI_IOMAP
79 select GENERIC_SCHED_CLOCK
80 select GENERIC_SMP_IDLE_THREAD
81 select HARDIRQS_SW_RESEND
82 select HAS_IOPORT
83 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
84 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
85 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
86 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL
87 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
88 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
89 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
90 select HAVE_ARCH_MMAP_RND_BITS if MMU
91 select HAVE_ARCH_PFN_VALID
92 select HAVE_ARCH_SECCOMP
93 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
94 select HAVE_ARCH_STACKLEAK
95 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
96 select HAVE_ARCH_TRACEHOOK
97 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
98 select HAVE_ARM_SMCCC if CPU_V7
99 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
100 select HAVE_CONTEXT_TRACKING_USER
101 select HAVE_C_RECORDMCOUNT
102 select HAVE_BUILDTIME_MCOUNT_SORT
103 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
104 select HAVE_DMA_CONTIGUOUS if MMU
105 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
106 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
107 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
108 select HAVE_EXIT_THREAD
109 select HAVE_GUP_FAST if ARM_LPAE
110 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
111 select HAVE_FUNCTION_ERROR_INJECTION
112 select HAVE_FUNCTION_GRAPH_TRACER
113 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
114 select HAVE_GCC_PLUGINS
115 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
116 select HAVE_IRQ_TIME_ACCOUNTING
117 select HAVE_KERNEL_GZIP
118 select HAVE_KERNEL_LZ4
119 select HAVE_KERNEL_LZMA
120 select HAVE_KERNEL_LZO
121 select HAVE_KERNEL_XZ
122 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
123 select HAVE_KRETPROBES if HAVE_KPROBES
124 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if (LD_VERSION >= 23600 || LD_IS_LLD)
125 select HAVE_MOD_ARCH_SPECIFIC
126 select HAVE_NMI
127 select HAVE_OPTPROBES if !THUMB2_KERNEL
128 select HAVE_PAGE_SIZE_4KB
129 select HAVE_PCI if MMU
130 select HAVE_PERF_EVENTS
131 select HAVE_PERF_REGS
132 select HAVE_PERF_USER_STACK_DUMP
133 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
134 select HAVE_REGS_AND_STACK_ACCESS_API
135 select HAVE_RSEQ
136 select HAVE_STACKPROTECTOR
137 select HAVE_SYSCALL_TRACEPOINTS
138 select HAVE_UID16
139 select HAVE_VIRT_CPU_ACCOUNTING_GEN
140 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
141 select IRQ_FORCED_THREADING
142 select LOCK_MM_AND_FIND_VMA
143 select MODULES_USE_ELF_REL
144 select NEED_DMA_MAP_STATE
145 select OF_EARLY_FLATTREE if OF
146 select OLD_SIGACTION
147 select OLD_SIGSUSPEND3
148 select PCI_DOMAINS_GENERIC if PCI
149 select PCI_SYSCALL if PCI
150 select PERF_USE_VMALLOC
151 select RTC_LIB
152 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC)
153 select SYS_SUPPORTS_APM_EMULATION
154 select THREAD_INFO_IN_TASK
155 select TIMER_OF if OF
156 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS
157 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
158 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
162 The ARM series is a line of low-power-consumption RISC chip designs
164 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
165 manufactured, but legacy ARM-based PC hardware remains popular in
176 supported in LLD until version 14. The combined range is -/+ 256 MiB,
182 select NEED_SG_DMA_LENGTH
210 select GENERIC_ALLOCATOR
269 Patch phys-to-virt and virt-to-phys translation functions at
273 This can only be used with non-XIP MMU kernels where the base
283 Select this when mach/io.h is required to provide special
290 Select this when mach/memory.h is required to provide special
319 bool "MMU-based Paged Memory Management Support"
322 Select if you want MMU-based virtualised addressing space
327 select ARM_NVIC
328 select CPU_V7M
329 select NO_IOPORT_MAP
357 # This is sorted alphabetically by mach-* pathname. However, plat-*
359 # plat- suffix) or along side the corresponding mach-* source.
361 source "arch/arm/mach-actions/Kconfig"
363 source "arch/arm/mach-alpine/Kconfig"
365 source "arch/arm/mach-artpec/Kconfig"
367 source "arch/arm/mach-aspeed/Kconfig"
369 source "arch/arm/mach-at91/Kconfig"
371 source "arch/arm/mach-axxia/Kconfig"
373 source "arch/arm/mach-bcm/Kconfig"
375 source "arch/arm/mach-berlin/Kconfig"
377 source "arch/arm/mach-clps711x/Kconfig"
379 source "arch/arm/mach-davinci/Kconfig"
381 source "arch/arm/mach-digicolor/Kconfig"
383 source "arch/arm/mach-dove/Kconfig"
385 source "arch/arm/mach-ep93xx/Kconfig"
387 source "arch/arm/mach-exynos/Kconfig"
389 source "arch/arm/mach-footbridge/Kconfig"
391 source "arch/arm/mach-gemini/Kconfig"
393 source "arch/arm/mach-highbank/Kconfig"
395 source "arch/arm/mach-hisi/Kconfig"
397 source "arch/arm/mach-hpe/Kconfig"
399 source "arch/arm/mach-imx/Kconfig"
401 source "arch/arm/mach-ixp4xx/Kconfig"
403 source "arch/arm/mach-keystone/Kconfig"
405 source "arch/arm/mach-lpc32xx/Kconfig"
407 source "arch/arm/mach-mediatek/Kconfig"
409 source "arch/arm/mach-meson/Kconfig"
411 source "arch/arm/mach-milbeaut/Kconfig"
413 source "arch/arm/mach-mmp/Kconfig"
415 source "arch/arm/mach-mstar/Kconfig"
417 source "arch/arm/mach-mv78xx0/Kconfig"
419 source "arch/arm/mach-mvebu/Kconfig"
421 source "arch/arm/mach-mxs/Kconfig"
423 source "arch/arm/mach-nomadik/Kconfig"
425 source "arch/arm/mach-npcm/Kconfig"
427 source "arch/arm/mach-omap1/Kconfig"
429 source "arch/arm/mach-omap2/Kconfig"
431 source "arch/arm/mach-orion5x/Kconfig"
433 source "arch/arm/mach-pxa/Kconfig"
435 source "arch/arm/mach-qcom/Kconfig"
437 source "arch/arm/mach-realtek/Kconfig"
439 source "arch/arm/mach-rpc/Kconfig"
441 source "arch/arm/mach-rockchip/Kconfig"
443 source "arch/arm/mach-s3c/Kconfig"
445 source "arch/arm/mach-s5pv210/Kconfig"
447 source "arch/arm/mach-sa1100/Kconfig"
449 source "arch/arm/mach-shmobile/Kconfig"
451 source "arch/arm/mach-socfpga/Kconfig"
453 source "arch/arm/mach-spear/Kconfig"
455 source "arch/arm/mach-sti/Kconfig"
457 source "arch/arm/mach-stm32/Kconfig"
459 source "arch/arm/mach-sunxi/Kconfig"
461 source "arch/arm/mach-tegra/Kconfig"
463 source "arch/arm/mach-ux500/Kconfig"
465 source "arch/arm/mach-versatile/Kconfig"
467 source "arch/arm/mach-vt8500/Kconfig"
469 source "arch/arm/mach-zynq/Kconfig"
471 # ARMv7-M architecture
475 select ARCH_HAS_RESET_CONTROLLER
476 select ARM_AMBA
477 select CLKSRC_LPC32XX
478 select PINCTRL
480 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
486 select ARM_AMBA
487 select CLKSRC_MPS2
489 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
490 with a range of available cores like Cortex-M3/M4/M7.
501 select CLKSRC_MMIO
502 select GENERIC_IRQ_CHIP
503 select IRQ_DOMAIN
507 select PLAT_ORION
523 source "arch/arm/Kconfig-nommu"
541 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
544 Executing a SWP instruction to read-only memory does not set bit 11
562 This option enables the workaround for the 430973 Cortex-A8
565 same virtual address, whether due to self-modifying code or virtual
566 to physical address re-mapping, Cortex-A8 does not recover from the
567 stale interworking branch prediction. This results in Cortex-A8
572 available in non-secure mode.
579 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
586 register may not be available in non-secure mode and thus is not
595 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
599 workaround disables the write-allocate mode for the L2 cache via the
601 may not be available in non-secure mode and thus is not available on
610 This option enables the workaround for the 742230 Cortex-A9
614 the diagnostic register of the Cortex-A9 which causes the DMB
617 register may not be available in non-secure mode and thus is not
626 This option enables the workaround for the 742231 Cortex-A9
628 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
633 register of the Cortex-A9 which reduces the linefill issuing
635 diagnostics register may not be available in non-secure mode and thus
644 This option enables the workaround for the 643719 Cortex-A9 (prior to
654 This option enables the workaround for the 720789 Cortex-A9 (prior to
667 This option enables the workaround for the 743622 Cortex-A9
669 optimisation in the Cortex-A9 Store Buffer may lead to data
671 register of the Cortex-A9 which disables the Store Buffer
675 may not be available in non-secure mode and thus is not available on a
683 This option enables the workaround for the 751472 Cortex-A9 (prior
689 not be available in non-secure mode and thus is not available on
697 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
700 can populate the micro-TLB with a stale entry which may be hit with
708 This option enables the workaround for the 754327 Cortex-A9 (prior to
716 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
721 hit-under-miss enabled). It sets the undocumented bit 31 in
723 register, thus disabling hit-under-miss without putting the
732 affecting Cortex-A9 MPCore with two or more processors (all
745 This option enables the workaround for the 764319 Cortex-A9 erratum.
750 way the kernel does not stop execution.
756 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
763 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
766 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
776 This option enables the workaround for the 773022 Cortex-A15
786 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
788 - Cortex-A12 852422: Execution of a sequence of instructions might
790 any Cortex-A12 cores yet.
799 This option enables the workaround for the 821420 Cortex-A12
803 deadlock when the VMOV instructions are issued out-of-order.
809 This option enables the workaround for the 825619 Cortex-A12
812 and Device/Strongly-Ordered loads and stores might cause deadlock
818 This option enables the workaround for the 857271 Cortex-A12
826 This option enables the workaround for the 852421 Cortex-A17
836 - Cortex-A17 852423: Execution of a sequence of instructions might
838 any Cortex-A17 cores yet.
839 This is identical to Cortex-A12 erratum 852422. It is a separate
840 config option from the A12 erratum due to the way errata are checked
847 This option enables the workaround for the 857272 Cortex-A17 erratum.
849 This is identical to Cortex-A12 erratum 857271. It is a separate
850 config option from the A12 erratum due to the way errata are checked
863 name of a bus system, i.e. the way the CPU talks to the other stuff
868 # Select ISA DMA interface
873 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
879 However, because of this erratum, an L2 set/way cache maintenance
880 operation can overtake an L1 set/way cache maintenance operation.
881 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
891 This option should be selected by machines which have an SMP-
894 The only effect of this option is to make the SMP-related
898 bool "Symmetric Multi-Processing"
902 select IRQ_WORK
908 If you say N here, the kernel will run on uni- and multiprocessor
914 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
915 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
916 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
925 SMP kernels contain instructions which fail on non-SMP processors.
939 select HAVE_IRQ_EXIT_ON_IRQ_STACK
940 select HAVE_SOFTIRQ_ON_OWN_STACK
952 bool "Multi-core scheduler support"
955 Multi-core scheduler support improves the CPU scheduler's decision
956 making when dealing with multi-core CPU chips at a cost of slightly
975 select ARM_ARCH_TIMER
985 bool "Multi-Cluster Power Management"
989 for (multi-)cluster based systems, such as big.LITTLE based
998 Platforms with 3 or 4 clusters that use MCPM must select this
1004 select MCPM
1012 select CPU_PM
1031 Select the desired split between kernel and user memory.
1065 int "Maximum number of CPUs (2-32)"
1073 debugging is enabled, which uses half of the per-CPU fixmap
1077 bool "Support for hot-pluggable CPUs"
1079 select GENERIC_IRQ_MIGRATION
1087 select ARM_PSCI_FW
1090 implementing the PSCI specification for CPU-centric power
1138 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1141 select ARM_UNWIND
1144 Thumb-2 mode.
1195 selected, since there is no way yet to sensibly distinguish
1212 select SPARSEMEM_STATIC if SPARSEMEM
1217 select KMAP_LOCAL
1218 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY
1234 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1242 user-space 2nd level page tables to reside in high memory.
1245 bool "Enable privileged no-access"
1251 use-after-free bugs becoming an exploitable privilege escalation
1262 Enable use of CPU domains to implement privileged no-access.
1264 CPUs with low-vector mappings use a best-efforts implementation.
1272 Enable privileged no-access by disabling TTBR0 page table walks when
1282 select KASAN_VMALLOC if KASAN
1294 Disabling this is usually safe for small single-platform
1314 select HAVE_PROC_CPU if PROC_FS
1318 address divisible by 4. On 32-bit ARM processors, these non-aligned
1321 correct operation of some network protocols. With an IP-only
1330 cores where a 8-word STM instruction give significantly higher
1337 However, if the CPU data cache is using a write-allocate mode,
1349 select PARAVIRT
1351 Select this option to enable fine granularity task steal time
1368 select ARCH_DMA_ADDR_T_64BIT
1369 select ARM_PSCI
1370 select SWIOTLB
1371 select SWIOTLB_XEN
1372 select PARAVIRT
1377 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1383 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS
1401 select IRQ_DOMAIN
1402 select OF
1413 This is the traditional way of passing data to the kernel at boot
1419 bool "Provide old way to pass kernel parameters"
1423 Some old boot loaders still use this way.
1431 The physical address at which the ROM-able zImage is to be
1433 ROM-able zImage formats normally set this to a suitable
1443 for the ROM-able zImage which must be available while the
1446 Platforms which normally make use of ROM-able zImage formats
1499 Uses the command-line options passed by the boot loader instead of
1506 The command-line arguments provided by the boot loader will be
1515 On some architectures (e.g. CATS), there is currently no way
1517 architectures, you should supply some command-line options at build
1529 Uses the command-line options passed by the boot loader. If
1536 The command-line arguments provided by the boot loader will be
1545 command-line options your boot loader passes to the kernel.
1549 bool "Kernel Execute-In-Place from ROM"
1553 Execute-In-Place allows the kernel to run from non-volatile storage
1556 to RAM. Read-write sections, such as the data section and stack,
1582 select ZLIB_INFLATE
1613 will be determined at run-time, either by masking the current IP
1624 select UCS2_STRING
1625 select EFI_PARAMS_FROM_FDT
1626 select EFI_STUB
1627 select EFI_GENERIC_STUB
1628 select EFI_RUNTIME_WRAPPERS
1631 by UEFI firmware (such as non-volatile variables, realtime
1646 continue to boot on existing non-UEFI platforms.
1652 to be enabled much earlier than we do on ARM, which is non-trivial.
1675 your machine has an FPA or floating point co-processor podule.
1684 Say Y to include 80-bit support in the kernel floating-point
1685 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1686 Note that gcc does not generate 80-bit operations by default,
1699 It is very simple, and approximately 3-6 times faster than NWFPE.
1707 bool "VFP-format floating point maths"
1713 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for