Lines Matching +full:fiq +full:- +full:based
1 # SPDX-License-Identifier: GPL-2.0
159 The ARM series is a line of low-power-consumption RISC chip designs
161 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
162 manufactured, but legacy ARM-based PC hardware remains popular in
173 supported in LLD until version 14. The combined range is -/+ 256 MiB,
255 config FIQ
266 Patch phys-to-virt and virt-to-phys translation functions at
270 This can only be used with non-XIP MMU kernels where the base
316 bool "MMU-based Paged Memory Management Support"
319 Select if you want MMU-based virtualised addressing space
354 # This is sorted alphabetically by mach-* pathname. However, plat-*
356 # plat- suffix) or along side the corresponding mach-* source.
358 source "arch/arm/mach-actions/Kconfig"
360 source "arch/arm/mach-alpine/Kconfig"
362 source "arch/arm/mach-artpec/Kconfig"
364 source "arch/arm/mach-aspeed/Kconfig"
366 source "arch/arm/mach-at91/Kconfig"
368 source "arch/arm/mach-axxia/Kconfig"
370 source "arch/arm/mach-bcm/Kconfig"
372 source "arch/arm/mach-berlin/Kconfig"
374 source "arch/arm/mach-clps711x/Kconfig"
376 source "arch/arm/mach-davinci/Kconfig"
378 source "arch/arm/mach-digicolor/Kconfig"
380 source "arch/arm/mach-dove/Kconfig"
382 source "arch/arm/mach-ep93xx/Kconfig"
384 source "arch/arm/mach-exynos/Kconfig"
386 source "arch/arm/mach-footbridge/Kconfig"
388 source "arch/arm/mach-gemini/Kconfig"
390 source "arch/arm/mach-highbank/Kconfig"
392 source "arch/arm/mach-hisi/Kconfig"
394 source "arch/arm/mach-hpe/Kconfig"
396 source "arch/arm/mach-imx/Kconfig"
398 source "arch/arm/mach-ixp4xx/Kconfig"
400 source "arch/arm/mach-keystone/Kconfig"
402 source "arch/arm/mach-lpc32xx/Kconfig"
404 source "arch/arm/mach-mediatek/Kconfig"
406 source "arch/arm/mach-meson/Kconfig"
408 source "arch/arm/mach-milbeaut/Kconfig"
410 source "arch/arm/mach-mmp/Kconfig"
412 source "arch/arm/mach-mstar/Kconfig"
414 source "arch/arm/mach-mv78xx0/Kconfig"
416 source "arch/arm/mach-mvebu/Kconfig"
418 source "arch/arm/mach-mxs/Kconfig"
420 source "arch/arm/mach-nomadik/Kconfig"
422 source "arch/arm/mach-npcm/Kconfig"
424 source "arch/arm/mach-omap1/Kconfig"
426 source "arch/arm/mach-omap2/Kconfig"
428 source "arch/arm/mach-orion5x/Kconfig"
430 source "arch/arm/mach-pxa/Kconfig"
432 source "arch/arm/mach-qcom/Kconfig"
434 source "arch/arm/mach-realtek/Kconfig"
436 source "arch/arm/mach-rpc/Kconfig"
438 source "arch/arm/mach-rockchip/Kconfig"
440 source "arch/arm/mach-s3c/Kconfig"
442 source "arch/arm/mach-s5pv210/Kconfig"
444 source "arch/arm/mach-sa1100/Kconfig"
446 source "arch/arm/mach-shmobile/Kconfig"
448 source "arch/arm/mach-socfpga/Kconfig"
450 source "arch/arm/mach-spear/Kconfig"
452 source "arch/arm/mach-sti/Kconfig"
454 source "arch/arm/mach-stm32/Kconfig"
456 source "arch/arm/mach-sunxi/Kconfig"
458 source "arch/arm/mach-tegra/Kconfig"
460 source "arch/arm/mach-ux500/Kconfig"
462 source "arch/arm/mach-versatile/Kconfig"
464 source "arch/arm/mach-vt8500/Kconfig"
466 source "arch/arm/mach-zynq/Kconfig"
468 # ARMv7-M architecture
477 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
486 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
487 with a range of available cores like Cortex-M3/M4/M7.
520 source "arch/arm/Kconfig-nommu"
538 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
541 Executing a SWP instruction to read-only memory does not set bit 11
559 This option enables the workaround for the 430973 Cortex-A8
562 same virtual address, whether due to self-modifying code or virtual
563 to physical address re-mapping, Cortex-A8 does not recover from the
564 stale interworking branch prediction. This results in Cortex-A8
569 available in non-secure mode.
576 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
583 register may not be available in non-secure mode and thus is not
592 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
596 workaround disables the write-allocate mode for the L2 cache via the
598 may not be available in non-secure mode and thus is not available on
607 This option enables the workaround for the 742230 Cortex-A9
611 the diagnostic register of the Cortex-A9 which causes the DMB
614 register may not be available in non-secure mode and thus is not
623 This option enables the workaround for the 742231 Cortex-A9
625 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
630 register of the Cortex-A9 which reduces the linefill issuing
632 diagnostics register may not be available in non-secure mode and thus
641 This option enables the workaround for the 643719 Cortex-A9 (prior to
651 This option enables the workaround for the 720789 Cortex-A9 (prior to
664 This option enables the workaround for the 743622 Cortex-A9
666 optimisation in the Cortex-A9 Store Buffer may lead to data
668 register of the Cortex-A9 which disables the Store Buffer
672 may not be available in non-secure mode and thus is not available on a
680 This option enables the workaround for the 751472 Cortex-A9 (prior
686 not be available in non-secure mode and thus is not available on
694 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
697 can populate the micro-TLB with a stale entry which may be hit with
705 This option enables the workaround for the 754327 Cortex-A9 (prior to
713 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
718 hit-under-miss enabled). It sets the undocumented bit 31 in
720 register, thus disabling hit-under-miss without putting the
729 affecting Cortex-A9 MPCore with two or more processors (all
742 This option enables the workaround for the 764319 Cortex-A9 erratum.
753 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
760 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
763 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
773 This option enables the workaround for the 773022 Cortex-A15
783 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
785 - Cortex-A12 852422: Execution of a sequence of instructions might
787 any Cortex-A12 cores yet.
796 This option enables the workaround for the 821420 Cortex-A12
800 deadlock when the VMOV instructions are issued out-of-order.
806 This option enables the workaround for the 825619 Cortex-A12
809 and Device/Strongly-Ordered loads and stores might cause deadlock
815 This option enables the workaround for the 857271 Cortex-A12
823 This option enables the workaround for the 852421 Cortex-A17
833 - Cortex-A17 852423: Execution of a sequence of instructions might
835 any Cortex-A17 cores yet.
836 This is identical to Cortex-A12 erratum 852422. It is a separate
844 This option enables the workaround for the 857272 Cortex-A17 erratum.
846 This is identical to Cortex-A12 erratum 857271. It is a separate
878 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
888 This option should be selected by machines which have an SMP-
891 The only effect of this option is to make the SMP-related
895 bool "Symmetric Multi-Processing"
905 If you say N here, the kernel will run on uni- and multiprocessor
911 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
912 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
913 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
922 SMP kernels contain instructions which fail on non-SMP processors.
949 bool "Multi-core scheduler support"
952 Multi-core scheduler support improves the CPU scheduler's decision
953 making when dealing with multi-core CPU chips at a cost of slightly
982 bool "Multi-Cluster Power Management"
986 for (multi-)cluster based systems, such as big.LITTLE based
1062 int "Maximum number of CPUs (2-32)"
1070 debugging is enabled, which uses half of the per-CPU fixmap
1074 bool "Support for hot-pluggable CPUs"
1087 implementing the PSCI specification for CPU-centric power
1135 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1141 Thumb-2 mode.
1231 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1239 user-space 2nd level page tables to reside in high memory.
1242 bool "Enable privileged no-access"
1248 use-after-free bugs becoming an exploitable privilege escalation
1259 Enable use of CPU domains to implement privileged no-access.
1261 CPUs with low-vector mappings use a best-efforts implementation.
1269 Enable privileged no-access by disabling TTBR0 page table walks when
1291 Disabling this is usually safe for small single-platform
1315 address divisible by 4. On 32-bit ARM processors, these non-aligned
1318 correct operation of some network protocols. With an IP-only
1327 cores where a 8-word STM instruction give significantly higher
1334 However, if the CPU data cache is using a write-allocate mode,
1374 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1428 The physical address at which the ROM-able zImage is to be
1430 ROM-able zImage formats normally set this to a suitable
1440 for the ROM-able zImage which must be available while the
1443 Platforms which normally make use of ROM-able zImage formats
1496 Uses the command-line options passed by the boot loader instead of
1503 The command-line arguments provided by the boot loader will be
1514 architectures, you should supply some command-line options at build
1526 Uses the command-line options passed by the boot loader. If
1533 The command-line arguments provided by the boot loader will be
1542 command-line options your boot loader passes to the kernel.
1546 bool "Kernel Execute-In-Place from ROM"
1550 Execute-In-Place allows the kernel to run from non-volatile storage
1553 to RAM. Read-write sections, such as the data section and stack,
1610 will be determined at run-time, either by masking the current IP
1628 by UEFI firmware (such as non-volatile variables, realtime
1643 continue to boot on existing non-UEFI platforms.
1649 to be enabled much earlier than we do on ARM, which is non-trivial.
1672 your machine has an FPA or floating point co-processor podule.
1681 Say Y to include 80-bit support in the kernel floating-point
1682 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1683 Note that gcc does not generate 80-bit operations by default,
1696 It is very simple, and approximately 3-6 times faster than NWFPE.
1704 bool "VFP-format floating point maths"
1710 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for