Lines Matching +full:config +full:- +full:space
1 # SPDX-License-Identifier: GPL-2.0
2 config ARM
47 # https://github.com/llvm/llvm-project/commit/d130f402642fba3d065aacb506cb061c899558de
164 The ARM series is a line of low-power-consumption RISC chip designs
166 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
167 manufactured, but legacy ARM-based PC hardware remains popular in
171 config ARM_HAS_GROUP_RELOCS
175 relocations. The combined range is -/+ 256 MiB, which is usually
179 config ARM_DMA_USE_IOMMU
185 config ARM_DMA_IOMMU_ALIGNMENT
193 for larger buffers it just a waste of address space. Drivers which has
195 virtual space with just a few allocations.
204 config SYS_SUPPORTS_APM_EMULATION
207 config HAVE_TCM
211 config HAVE_PROC_CPU
214 config NO_IOPORT_MAP
217 config SBUS
220 config STACKTRACE_SUPPORT
224 config LOCKDEP_SUPPORT
228 config ARCH_HAS_ILOG2_U32
231 config ARCH_HAS_ILOG2_U64
234 config ARCH_HAS_BANDGAP
237 config FIX_EARLYCON_MEM
240 config GENERIC_HWEIGHT
244 config GENERIC_CALIBRATE_DELAY
248 config ARCH_MAY_HAVE_PC_FDC
251 config ARCH_SUPPORTS_UPROBES
254 config GENERIC_ISA_DMA
257 config FIQ
260 config ARCH_MTD_XIP
263 config ARM_PATCH_PHYS_VIRT
268 Patch phys-to-virt and virt-to-phys translation functions at
272 This can only be used with non-XIP MMU kernels where the base
279 config NEED_MACH_IO_H
286 config NEED_MACH_MEMORY_H
293 config PHYS_OFFSET
306 config GENERIC_BUG
310 config PGTABLE_LEVELS
317 config MMU
318 bool "MMU-based Paged Memory Management Support"
321 Select if you want MMU-based virtualised addressing space
324 config ARM_SINGLE_ARMV7M
330 config ARCH_MMAP_RND_BITS_MIN
333 config ARCH_MMAP_RND_BITS_MAX
338 config ARCH_MULTIPLATFORM
356 # This is sorted alphabetically by mach-* pathname. However, plat-*
358 # plat- suffix) or along side the corresponding mach-* source.
360 source "arch/arm/mach-actions/Kconfig"
362 source "arch/arm/mach-alpine/Kconfig"
364 source "arch/arm/mach-artpec/Kconfig"
366 source "arch/arm/mach-aspeed/Kconfig"
368 source "arch/arm/mach-at91/Kconfig"
370 source "arch/arm/mach-axxia/Kconfig"
372 source "arch/arm/mach-bcm/Kconfig"
374 source "arch/arm/mach-berlin/Kconfig"
376 source "arch/arm/mach-clps711x/Kconfig"
378 source "arch/arm/mach-davinci/Kconfig"
380 source "arch/arm/mach-digicolor/Kconfig"
382 source "arch/arm/mach-dove/Kconfig"
384 source "arch/arm/mach-ep93xx/Kconfig"
386 source "arch/arm/mach-exynos/Kconfig"
388 source "arch/arm/mach-footbridge/Kconfig"
390 source "arch/arm/mach-gemini/Kconfig"
392 source "arch/arm/mach-highbank/Kconfig"
394 source "arch/arm/mach-hisi/Kconfig"
396 source "arch/arm/mach-imx/Kconfig"
398 source "arch/arm/mach-ixp4xx/Kconfig"
400 source "arch/arm/mach-keystone/Kconfig"
402 source "arch/arm/mach-lpc32xx/Kconfig"
404 source "arch/arm/mach-mediatek/Kconfig"
406 source "arch/arm/mach-meson/Kconfig"
408 source "arch/arm/mach-milbeaut/Kconfig"
410 source "arch/arm/mach-mmp/Kconfig"
412 source "arch/arm/mach-mstar/Kconfig"
414 source "arch/arm/mach-mv78xx0/Kconfig"
416 source "arch/arm/mach-mvebu/Kconfig"
418 source "arch/arm/mach-mxs/Kconfig"
420 source "arch/arm/mach-nomadik/Kconfig"
422 source "arch/arm/mach-npcm/Kconfig"
424 source "arch/arm/mach-omap1/Kconfig"
426 source "arch/arm/mach-omap2/Kconfig"
428 source "arch/arm/mach-orion5x/Kconfig"
430 source "arch/arm/mach-pxa/Kconfig"
432 source "arch/arm/mach-qcom/Kconfig"
434 source "arch/arm/mach-realtek/Kconfig"
436 source "arch/arm/mach-rpc/Kconfig"
438 source "arch/arm/mach-rockchip/Kconfig"
440 source "arch/arm/mach-s3c/Kconfig"
442 source "arch/arm/mach-s5pv210/Kconfig"
444 source "arch/arm/mach-sa1100/Kconfig"
446 source "arch/arm/mach-shmobile/Kconfig"
448 source "arch/arm/mach-socfpga/Kconfig"
450 source "arch/arm/mach-spear/Kconfig"
452 source "arch/arm/mach-sti/Kconfig"
454 source "arch/arm/mach-stm32/Kconfig"
456 source "arch/arm/mach-sunxi/Kconfig"
458 source "arch/arm/mach-tegra/Kconfig"
460 source "arch/arm/mach-ux500/Kconfig"
462 source "arch/arm/mach-versatile/Kconfig"
464 source "arch/arm/mach-vt8500/Kconfig"
466 source "arch/arm/mach-zynq/Kconfig"
468 # ARMv7-M architecture
469 config ARCH_LPC18XX
477 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
480 config ARCH_MPS2
486 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
487 with a range of available cores like Cortex-M3/M4/M7.
493 config ARCH_ACORN
496 config PLAT_ORION
502 config PLAT_ORION_LEGACY
506 config PLAT_VERSATILE
511 config IWMMXT
520 source "arch/arm/Kconfig-nommu"
523 config PJ4B_ERRATA_4742
537 config ARM_ERRATA_326103
538 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
541 Executing a SWP instruction to read-only memory does not set bit 11
546 config ARM_ERRATA_411920
555 config ARM_ERRATA_430973
559 This option enables the workaround for the 430973 Cortex-A8
562 same virtual address, whether due to self-modifying code or virtual
563 to physical address re-mapping, Cortex-A8 does not recover from the
564 stale interworking branch prediction. This results in Cortex-A8
569 available in non-secure mode.
571 config ARM_ERRATA_458693
576 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
583 register may not be available in non-secure mode and thus is not
587 config ARM_ERRATA_460075
592 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
596 workaround disables the write-allocate mode for the L2 cache via the
598 may not be available in non-secure mode and thus is not available on
602 config ARM_ERRATA_742230
607 This option enables the workaround for the 742230 Cortex-A9
611 the diagnostic register of the Cortex-A9 which causes the DMB
614 register may not be available in non-secure mode and thus is not
618 config ARM_ERRATA_742231
623 This option enables the workaround for the 742231 Cortex-A9
625 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
630 register of the Cortex-A9 which reduces the linefill issuing
632 diagnostics register may not be available in non-secure mode and thus
636 config ARM_ERRATA_643719
641 This option enables the workaround for the 643719 Cortex-A9 (prior to
647 config ARM_ERRATA_720789
651 This option enables the workaround for the 720789 Cortex-A9 (prior to
659 config ARM_ERRATA_743622
664 This option enables the workaround for the 743622 Cortex-A9
666 optimisation in the Cortex-A9 Store Buffer may lead to data
668 register of the Cortex-A9 which disables the Store Buffer
672 may not be available in non-secure mode and thus is not available on a
675 config ARM_ERRATA_751472
680 This option enables the workaround for the 751472 Cortex-A9 (prior
686 not be available in non-secure mode and thus is not available on
690 config ARM_ERRATA_754322
694 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
697 can populate the micro-TLB with a stale entry which may be hit with
701 config ARM_ERRATA_754327
705 This option enables the workaround for the 754327 Cortex-A9 (prior to
712 config ARM_ERRATA_364296
713 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
718 hit-under-miss enabled). It sets the undocumented bit 31 in
720 register, thus disabling hit-under-miss without putting the
724 config ARM_ERRATA_764369
729 affecting Cortex-A9 MPCore with two or more processors (all
738 config ARM_ERRATA_764319
742 This option enables the workaround for the 764319 Cortex-A9 erratum.
749 config ARM_ERRATA_775420
753 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
759 config ARM_ERRATA_798181
760 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
763 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
769 config ARM_ERRATA_773022
773 This option enables the workaround for the 773022 Cortex-A15
778 config ARM_ERRATA_818325_852422
783 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
785 - Cortex-A12 852422: Execution of a sequence of instructions might
787 any Cortex-A12 cores yet.
792 config ARM_ERRATA_821420
796 This option enables the workaround for the 821420 Cortex-A12
800 deadlock when the VMOV instructions are issued out-of-order.
802 config ARM_ERRATA_825619
806 This option enables the workaround for the 825619 Cortex-A12
809 and Device/Strongly-Ordered loads and stores might cause deadlock
811 config ARM_ERRATA_857271
815 This option enables the workaround for the 857271 Cortex-A12
819 config ARM_ERRATA_852421
823 This option enables the workaround for the 852421 Cortex-A17
828 config ARM_ERRATA_852423
833 - Cortex-A17 852423: Execution of a sequence of instructions might
835 any Cortex-A17 cores yet.
836 This is identical to Cortex-A12 erratum 852422. It is a separate
837 config option from the A12 erratum due to the way errata are checked
840 config ARM_ERRATA_857272
844 This option enables the workaround for the 857272 Cortex-A17 erratum.
846 This is identical to Cortex-A12 erratum 857271. It is a separate
847 config option from the A12 erratum due to the way errata are checked
856 config ISA
866 config ISA_DMA_API
869 config ARM_ERRATA_814220
878 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
885 config HAVE_SMP
888 This option should be selected by machines which have an SMP-
891 The only effect of this option is to make the SMP-related
894 config SMP
895 bool "Symmetric Multi-Processing"
905 If you say N here, the kernel will run on uni- and multiprocessor
911 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
912 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
913 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
917 config SMP_ON_UP
922 SMP kernels contain instructions which fail on non-SMP processors.
924 these instructions safe. Disabling it allows about 1K of space
930 config CURRENT_POINTER_IN_TPIDRURO
934 config IRQSTACKS
939 config ARM_CPU_TOPOLOGY
950 config HAVE_ARM_SCU
955 config HAVE_ARM_ARCH_TIMER
962 config HAVE_ARM_TWD
967 config MCPM
968 bool "Multi-Cluster Power Management"
972 for (multi-)cluster based systems, such as big.LITTLE based
975 config MCPM_QUAD_CLUSTER
984 config BIG_LITTLE
992 config BL_SWITCHER
1001 config BL_SWITCHER_DUMMY_IF
1019 config VMSPLIT_3G
1021 config VMSPLIT_3G_OPT
1024 config VMSPLIT_2G
1026 config VMSPLIT_1G
1030 config PAGE_OFFSET
1038 config KASAN_SHADOW_OFFSET
1047 config NR_CPUS
1048 int "Maximum number of CPUs (2-32)"
1056 debugging is enabled, which uses half of the per-CPU fixmap
1059 config HOTPLUG_CPU
1060 bool "Support for hot-pluggable CPUs"
1067 config ARM_PSCI
1073 implementing the PSCI specification for CPU-centric power
1078 config HZ_FIXED
1087 config HZ_100
1090 config HZ_200
1093 config HZ_250
1096 config HZ_300
1099 config HZ_500
1102 config HZ_1000
1107 config HZ
1117 config SCHED_HRTICK
1120 config THUMB2_KERNEL
1121 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1127 Thumb-2 mode.
1131 config ARM_PATCH_IDIV
1149 config AEABI
1156 space environment that is also compiled with EABI.
1166 config OABI_COMPAT
1181 If you know you'll be using only pure EABI user space then you
1187 config ARCH_SELECT_MEMORY_MODEL
1190 config ARCH_FLATMEM_ENABLE
1193 config ARCH_SPARSEMEM_ENABLE
1197 config HIGHMEM
1203 The address space of ARM processors is only 4 Gigabytes large
1204 and it has to accommodate user address space, kernel address
1205 space as well as some memory mapped IO. That means that, if you
1211 vmalloc space and actual amount of RAM, you may not need this
1216 config HIGHPTE
1217 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1225 user-space 2nd level page tables to reside in high memory.
1227 config ARM_PAN
1228 bool "Enable privileged no-access"
1234 use-after-free bugs becoming an exploitable privilege escalation
1241 config CPU_SW_DOMAIN_PAN
1245 Enable use of CPU domains to implement privileged no-access.
1247 CPUs with low-vector mappings use a best-efforts implementation.
1251 config CPU_TTBR0_PAN
1255 Enable privileged no-access by disabling TTBR0 page table walks when
1258 config HW_PERF_EVENTS
1262 config ARM_MODULE_PLTS
1277 Disabling this is usually safe for small single-platform
1280 config ARCH_FORCE_MAX_ORDER
1295 config ALIGNMENT_TRAP
1301 address divisible by 4. On 32-bit ARM processors, these non-aligned
1304 correct operation of some network protocols. With an IP-only
1307 config UACCESS_WITH_MEMCPY
1313 cores where a 8-word STM instruction give significantly higher
1317 between threads sharing the same address space if they invoke
1320 However, if the CPU data cache is using a write-allocate mode,
1323 config PARAVIRT
1330 config PARAVIRT_TIME_ACCOUNTING
1341 config XEN_DOM0
1345 config XEN
1359 config CC_HAVE_STACKPROTECTOR_TLS
1360 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1362 config STACKPROTECTOR_PER_TASK
1371 kernel's address space are forced to use the same canary value for
1381 config USE_OF
1388 config ARCH_WANT_FLAT_DTB_INSTALL
1391 config ATAGS
1400 config DEPRECATED_PARAM_STRUCT
1408 # TEXT and BSS so we preserve their values in the config files.
1409 config ZBOOT_ROM_TEXT
1413 The physical address at which the ROM-able zImage is to be
1415 ROM-able zImage formats normally set this to a suitable
1420 config ZBOOT_ROM_BSS
1425 for the ROM-able zImage which must be available while the
1428 Platforms which normally make use of ROM-able zImage formats
1433 config ZBOOT_ROM
1441 config ARM_APPENDED_DTB
1461 config ARM_ATAG_DTB_COMPAT
1478 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1481 Uses the command-line options passed by the boot loader instead of
1485 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1488 The command-line arguments provided by the boot loader will be
1493 config CMDLINE
1499 architectures, you should supply some command-line options at build
1508 config CMDLINE_FROM_BOOTLOADER
1511 Uses the command-line options passed by the boot loader. If
1515 config CMDLINE_EXTEND
1518 The command-line arguments provided by the boot loader will be
1521 config CMDLINE_FORCE
1527 command-line options your boot loader passes to the kernel.
1530 config XIP_KERNEL
1531 bool "Kernel Execute-In-Place from ROM"
1535 Execute-In-Place allows the kernel to run from non-volatile storage
1537 space since the text section of the kernel is not loaded from flash
1538 to RAM. Read-write sections, such as the data section and stack,
1540 it has to run directly from flash, so it will take more space to
1552 config XIP_PHYS_ADDR
1561 config XIP_DEFLATED_DATA
1569 copied, saving some precious ROM space. A possible drawback is a
1572 config ARCH_SUPPORTS_KEXEC
1575 config ATAGS_PROC
1583 config ARCH_SUPPORTS_CRASH_DUMP
1586 config ARCH_DEFAULT_CRASH_DUMP
1589 config AUTO_ZRELADDR
1595 will be determined at run-time, either by masking the current IP
1600 config EFI_STUB
1603 config EFI
1613 by UEFI firmware (such as non-volatile variables, realtime
1619 config DMI
1628 continue to boot on existing non-UEFI platforms.
1634 to be enabled much earlier than we do on ARM, which is non-trivial.
1650 config FPE_NWFPE
1657 your machine has an FPA or floating point co-processor podule.
1662 config FPE_NWFPE_XP
1666 Say Y to include 80-bit support in the kernel floating-point
1667 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1668 Note that gcc does not generate 80-bit operations by default,
1674 config FPE_FASTFPE
1681 It is very simple, and approximately 3-6 times faster than NWFPE.
1688 config VFP
1689 bool "VFP-format floating point maths"
1695 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for
1700 config VFPv3
1705 config NEON
1712 config KERNEL_MODE_NEON
1724 config ARCH_SUSPEND_POSSIBLE
1729 config ARM_CPU_SUSPEND
1733 config ARCH_HIBERNATION_POSSIBLE