Lines Matching +full:cpu +full:- +full:centric
1 # SPDX-License-Identifier: GPL-2.0
162 The ARM series is a line of low-power-consumption RISC chip designs
164 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
165 manufactured, but legacy ARM-based PC hardware remains popular in
173 relocations. The combined range is -/+ 256 MiB, which is usually
266 Patch phys-to-virt and virt-to-phys translation functions at
270 This can only be used with non-XIP MMU kernels where the base
316 bool "MMU-based Paged Memory Management Support"
319 Select if you want MMU-based virtualised addressing space
354 # This is sorted alphabetically by mach-* pathname. However, plat-*
356 # plat- suffix) or along side the corresponding mach-* source.
358 source "arch/arm/mach-actions/Kconfig"
360 source "arch/arm/mach-alpine/Kconfig"
362 source "arch/arm/mach-artpec/Kconfig"
364 source "arch/arm/mach-aspeed/Kconfig"
366 source "arch/arm/mach-at91/Kconfig"
368 source "arch/arm/mach-axxia/Kconfig"
370 source "arch/arm/mach-bcm/Kconfig"
372 source "arch/arm/mach-berlin/Kconfig"
374 source "arch/arm/mach-clps711x/Kconfig"
376 source "arch/arm/mach-davinci/Kconfig"
378 source "arch/arm/mach-digicolor/Kconfig"
380 source "arch/arm/mach-dove/Kconfig"
382 source "arch/arm/mach-ep93xx/Kconfig"
384 source "arch/arm/mach-exynos/Kconfig"
386 source "arch/arm/mach-footbridge/Kconfig"
388 source "arch/arm/mach-gemini/Kconfig"
390 source "arch/arm/mach-highbank/Kconfig"
392 source "arch/arm/mach-hisi/Kconfig"
394 source "arch/arm/mach-imx/Kconfig"
396 source "arch/arm/mach-ixp4xx/Kconfig"
398 source "arch/arm/mach-keystone/Kconfig"
400 source "arch/arm/mach-lpc32xx/Kconfig"
402 source "arch/arm/mach-mediatek/Kconfig"
404 source "arch/arm/mach-meson/Kconfig"
406 source "arch/arm/mach-milbeaut/Kconfig"
408 source "arch/arm/mach-mmp/Kconfig"
410 source "arch/arm/mach-mstar/Kconfig"
412 source "arch/arm/mach-mv78xx0/Kconfig"
414 source "arch/arm/mach-mvebu/Kconfig"
416 source "arch/arm/mach-mxs/Kconfig"
418 source "arch/arm/mach-nomadik/Kconfig"
420 source "arch/arm/mach-npcm/Kconfig"
422 source "arch/arm/mach-omap1/Kconfig"
424 source "arch/arm/mach-omap2/Kconfig"
426 source "arch/arm/mach-orion5x/Kconfig"
428 source "arch/arm/mach-pxa/Kconfig"
430 source "arch/arm/mach-qcom/Kconfig"
432 source "arch/arm/mach-realtek/Kconfig"
434 source "arch/arm/mach-rpc/Kconfig"
436 source "arch/arm/mach-rockchip/Kconfig"
438 source "arch/arm/mach-s3c/Kconfig"
440 source "arch/arm/mach-s5pv210/Kconfig"
442 source "arch/arm/mach-sa1100/Kconfig"
444 source "arch/arm/mach-shmobile/Kconfig"
446 source "arch/arm/mach-socfpga/Kconfig"
448 source "arch/arm/mach-spear/Kconfig"
450 source "arch/arm/mach-sti/Kconfig"
452 source "arch/arm/mach-stm32/Kconfig"
454 source "arch/arm/mach-sunxi/Kconfig"
456 source "arch/arm/mach-tegra/Kconfig"
458 source "arch/arm/mach-ux500/Kconfig"
460 source "arch/arm/mach-versatile/Kconfig"
462 source "arch/arm/mach-vt8500/Kconfig"
464 source "arch/arm/mach-zynq/Kconfig"
466 # ARMv7-M architecture
475 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
484 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
485 with a range of available cores like Cortex-M3/M4/M7.
515 running on a CPU that supports it.
518 source "arch/arm/Kconfig-nommu"
522 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
529 instructions. This sensitivity can result in a CPU hang scenario.
536 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
539 Executing a SWP instruction to read-only memory does not set bit 11
557 This option enables the workaround for the 430973 Cortex-A8
560 same virtual address, whether due to self-modifying code or virtual
561 to physical address re-mapping, Cortex-A8 does not recover from the
562 stale interworking branch prediction. This results in Cortex-A8
567 available in non-secure mode.
574 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
581 register may not be available in non-secure mode and thus is not
590 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
594 workaround disables the write-allocate mode for the L2 cache via the
596 may not be available in non-secure mode and thus is not available on
605 This option enables the workaround for the 742230 Cortex-A9
609 the diagnostic register of the Cortex-A9 which causes the DMB
612 register may not be available in non-secure mode and thus is not
621 This option enables the workaround for the 742231 Cortex-A9
623 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
626 replaced from one of the CPUs at the same time as another CPU is
628 register of the Cortex-A9 which reduces the linefill issuing
630 diagnostics register may not be available in non-secure mode and thus
639 This option enables the workaround for the 643719 Cortex-A9 (prior to
649 This option enables the workaround for the 720789 Cortex-A9 (prior to
662 This option enables the workaround for the 743622 Cortex-A9
664 optimisation in the Cortex-A9 Store Buffer may lead to data
666 register of the Cortex-A9 which disables the Store Buffer
670 may not be available in non-secure mode and thus is not available on a
678 This option enables the workaround for the 751472 Cortex-A9 (prior
681 operation is received by a CPU before the ICIALLUIS has completed,
684 not be available in non-secure mode and thus is not available on
692 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
695 can populate the micro-TLB with a stale entry which may be hit with
703 This option enables the workaround for the 754327 Cortex-A9 (prior to
711 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
716 hit-under-miss enabled). It sets the undocumented bit 31 in
718 register, thus disabling hit-under-miss without putting the
727 affecting Cortex-A9 MPCore with two or more processors (all
740 This option enables the workaround for the 764319 Cortex-A9 erratum.
751 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
758 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
761 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
771 This option enables the workaround for the 773022 Cortex-A15
781 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
783 - Cortex-A12 852422: Execution of a sequence of instructions might
784 lead to either a data corruption or a CPU deadlock. Not fixed in
785 any Cortex-A12 cores yet.
794 This option enables the workaround for the 821420 Cortex-A12
798 deadlock when the VMOV instructions are issued out-of-order.
804 This option enables the workaround for the 825619 Cortex-A12
807 and Device/Strongly-Ordered loads and stores might cause deadlock
810 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
813 This option enables the workaround for the 857271 Cortex-A12
814 (all revs) erratum. Under very rare timing conditions, the CPU might
821 This option enables the workaround for the 852421 Cortex-A17
831 - Cortex-A17 852423: Execution of a sequence of instructions might
832 lead to either a data corruption or a CPU deadlock. Not fixed in
833 any Cortex-A17 cores yet.
834 This is identical to Cortex-A12 erratum 852422. It is a separate
839 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
842 This option enables the workaround for the 857272 Cortex-A17 erratum.
844 This is identical to Cortex-A12 erratum 857271. It is a separate
858 name of a bus system, i.e. the way the CPU talks to the other stuff
876 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
886 This option should be selected by machines which have an SMP-
887 capable CPU.
889 The only effect of this option is to make the SMP-related
893 bool "Symmetric Multi-Processing"
899 This enables support for systems with more than one CPU. If you have
900 a system with only one CPU, say N. If you have a system with more
901 than one CPU, say Y.
903 If you say N here, the kernel will run on uni- and multiprocessor
904 machines, but will use only one CPU of a multiprocessor machine. If
909 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
910 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
911 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
920 SMP kernels contain instructions which fail on non-SMP processors.
938 bool "Support cpu topology definition"
944 Support ARM cpu topology definition. The MPIDR register defines
945 affinity between processors which is then used to describe the cpu
966 bool "Multi-Cluster Power Management"
970 for (multi-)cluster based systems, such as big.LITTLE based
1046 int "Maximum number of CPUs (2-32)"
1054 debugging is enabled, which uses half of the per-CPU fixmap
1058 bool "Support for hot-pluggable CPUs"
1063 can be controlled through /sys/devices/system/cpu.
1071 implementing the PSCI specification for CPU-centric power
1119 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1125 Thumb-2 mode.
1142 with the sdiv or udiv plus "bx lr" instructions when the CPU
1215 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1223 user-space 2nd level page tables to reside in high memory.
1226 bool "Enable privileged no-access"
1232 use-after-free bugs becoming an exploitable privilege escalation
1236 The implementation uses CPU domains when !CONFIG_ARM_LPAE and
1243 Enable use of CPU domains to implement privileged no-access.
1245 CPUs with low-vector mappings use a best-efforts implementation.
1253 Enable privileged no-access by disabling TTBR0 page table walks when
1275 Disabling this is usually safe for small single-platform
1299 address divisible by 4. On 32-bit ARM processors, these non-aligned
1302 correct operation of some network protocols. With an IP-only
1310 Implement faster copy_to_user and clear_user methods for CPU
1311 cores where a 8-word STM instruction give significantly higher
1318 However, if the CPU data cache is using a write-allocate mode,
1358 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1411 The physical address at which the ROM-able zImage is to be
1413 ROM-able zImage formats normally set this to a suitable
1423 for the ROM-able zImage which must be available while the
1426 Platforms which normally make use of ROM-able zImage formats
1479 Uses the command-line options passed by the boot loader instead of
1486 The command-line arguments provided by the boot loader will be
1497 architectures, you should supply some command-line options at build
1509 Uses the command-line options passed by the boot loader. If
1516 The command-line arguments provided by the boot loader will be
1525 command-line options your boot loader passes to the kernel.
1529 bool "Kernel Execute-In-Place from ROM"
1533 Execute-In-Place allows the kernel to run from non-volatile storage
1534 directly addressable by the CPU, such as NOR flash. This saves RAM
1536 to RAM. Read-write sections, such as the data section and stack,
1593 will be determined at run-time, either by masking the current IP
1611 by UEFI firmware (such as non-volatile variables, realtime
1626 continue to boot on existing non-UEFI platforms.
1632 to be enabled much earlier than we do on ARM, which is non-trivial.
1636 menu "CPU Power Management"
1655 your machine has an FPA or floating point co-processor podule.
1664 Say Y to include 80-bit support in the kernel floating-point
1665 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1666 Note that gcc does not generate 80-bit operations by default,
1679 It is very simple, and approximately 3-6 times faster than NWFPE.
1687 bool "VFP-format floating point maths"
1693 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for