Lines Matching +full:sm8650 +full:- +full:dp
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,snps-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wesley Cheng <quic_wcheng@quicinc.com>
19 const: qcom,snps-dwc3
21 - compatible
26 - enum:
27 - qcom,ipq4019-dwc3
28 - qcom,ipq5018-dwc3
29 - qcom,ipq5332-dwc3
30 - qcom,ipq5424-dwc3
31 - qcom,ipq6018-dwc3
32 - qcom,ipq8064-dwc3
33 - qcom,ipq8074-dwc3
34 - qcom,ipq9574-dwc3
35 - qcom,milos-dwc3
36 - qcom,msm8953-dwc3
37 - qcom,msm8994-dwc3
38 - qcom,msm8996-dwc3
39 - qcom,msm8998-dwc3
40 - qcom,qcm2290-dwc3
41 - qcom,qcs404-dwc3
42 - qcom,qcs615-dwc3
43 - qcom,qcs8300-dwc3
44 - qcom,qdu1000-dwc3
45 - qcom,sa8775p-dwc3
46 - qcom,sar2130p-dwc3
47 - qcom,sc7180-dwc3
48 - qcom,sc7280-dwc3
49 - qcom,sc8180x-dwc3
50 - qcom,sc8180x-dwc3-mp
51 - qcom,sc8280xp-dwc3
52 - qcom,sc8280xp-dwc3-mp
53 - qcom,sdm660-dwc3
54 - qcom,sdm670-dwc3
55 - qcom,sdm845-dwc3
56 - qcom,sdx55-dwc3
57 - qcom,sdx65-dwc3
58 - qcom,sdx75-dwc3
59 - qcom,sm4250-dwc3
60 - qcom,sm6115-dwc3
61 - qcom,sm6125-dwc3
62 - qcom,sm6350-dwc3
63 - qcom,sm6375-dwc3
64 - qcom,sm8150-dwc3
65 - qcom,sm8250-dwc3
66 - qcom,sm8350-dwc3
67 - qcom,sm8450-dwc3
68 - qcom,sm8550-dwc3
69 - qcom,sm8650-dwc3
70 - qcom,x1e80100-dwc3
71 - const: qcom,snps-dwc3
76 power-domains:
79 required-opps:
85 - cfg_noc:: System Config NOC clock.
86 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
88 - iface:: System bus AXI clock.
89 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low
91 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host
96 clock-names:
100 dma-coherent: true
111 interconnect-names:
113 - const: usb-ddr
114 - const: apps-usb
119 - dwc_usb3: Core DWC3 interrupt
120 - pwr_event: Used for wakeup based on other power events.
121 - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is
124 {dp/dm}_hs_phy_irq and qusb2_phy_irq.
125 - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and
130 - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/
132 only on SoCs with non-QUSB2 targets with
134 - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation.
138 interrupt-names:
142 qcom,select-utmi-as-pipe-clk:
149 wakeup-source: true
154 - compatible
155 - reg
156 - clocks
157 - clock-names
158 - interrupts
159 - interrupt-names
162 - $ref: snps,dwc3-common.yaml#
163 - if:
168 - qcom,ipq4019-dwc3
169 - qcom,ipq5332-dwc3
174 clock-names:
176 - const: core
177 - const: sleep
178 - const: mock_utmi
180 - if:
185 - qcom,ipq8064-dwc3
190 - description: Master/Core clock, has to be >= 125 MHz
192 clock-names:
194 - const: core
196 - if:
201 - qcom,ipq9574-dwc3
202 - qcom,msm8953-dwc3
203 - qcom,msm8996-dwc3
204 - qcom,msm8998-dwc3
205 - qcom,qcs8300-dwc3
206 - qcom,sa8775p-dwc3
207 - qcom,sc7180-dwc3
208 - qcom,sc7280-dwc3
209 - qcom,sdm670-dwc3
210 - qcom,sdm845-dwc3
211 - qcom,sdx55-dwc3
212 - qcom,sdx65-dwc3
213 - qcom,sdx75-dwc3
214 - qcom,sm6350-dwc3
219 clock-names:
221 - const: cfg_noc
222 - const: core
223 - const: iface
224 - const: sleep
225 - const: mock_utmi
227 - if:
232 - qcom,ipq6018-dwc3
238 clock-names:
240 - items:
241 - const: core
242 - const: sleep
243 - const: mock_utmi
244 - items:
245 - const: cfg_noc
246 - const: core
247 - const: sleep
248 - const: mock_utmi
250 - if:
255 - qcom,ipq8074-dwc3
256 - qcom,qdu1000-dwc3
261 clock-names:
263 - const: cfg_noc
264 - const: core
265 - const: sleep
266 - const: mock_utmi
268 - if:
273 - qcom,ipq5018-dwc3
274 - qcom,msm8994-dwc3
275 - qcom,qcs404-dwc3
280 clock-names:
282 - const: core
283 - const: iface
284 - const: sleep
285 - const: mock_utmi
287 - if:
292 - qcom,sc8280xp-dwc3
293 - qcom,sc8280xp-dwc3-mp
294 - qcom,x1e80100-dwc3
295 - qcom,x1e80100-dwc3-mp
300 clock-names:
302 - const: cfg_noc
303 - const: core
304 - const: iface
305 - const: sleep
306 - const: mock_utmi
307 - const: noc_aggr
308 - const: noc_aggr_north
309 - const: noc_aggr_south
310 - const: noc_sys
312 - if:
317 - qcom,sdm660-dwc3
323 clock-names:
325 - items:
326 - const: cfg_noc
327 - const: core
328 - const: iface
329 - const: sleep
330 - const: mock_utmi
331 - items:
332 - const: cfg_noc
333 - const: core
334 - const: sleep
335 - const: mock_utmi
337 - if:
342 - qcom,milos-dwc3
343 - qcom,qcm2290-dwc3
344 - qcom,qcs615-dwc3
345 - qcom,sar2130p-dwc3
346 - qcom,sc8180x-dwc3
347 - qcom,sc8180x-dwc3-mp
348 - qcom,sm6115-dwc3
349 - qcom,sm6125-dwc3
350 - qcom,sm8150-dwc3
351 - qcom,sm8250-dwc3
352 - qcom,sm8450-dwc3
353 - qcom,sm8550-dwc3
354 - qcom,sm8650-dwc3
359 clock-names:
361 - const: cfg_noc
362 - const: core
363 - const: iface
364 - const: sleep
365 - const: mock_utmi
366 - const: xo
368 - if:
373 - qcom,sm8350-dwc3
379 clock-names:
382 - const: cfg_noc
383 - const: core
384 - const: iface
385 - const: sleep
386 - const: mock_utmi
387 - const: xo
389 - if:
394 - qcom,ipq5018-dwc3
395 - qcom,ipq6018-dwc3
396 - qcom,ipq8074-dwc3
397 - qcom,msm8953-dwc3
398 - qcom,msm8998-dwc3
404 interrupt-names:
407 - const: dwc_usb3
408 - const: pwr_event
409 - const: qusb2_phy
410 - const: ss_phy_irq
412 - if:
417 - qcom,msm8996-dwc3
418 - qcom,qcs404-dwc3
419 - qcom,sdm660-dwc3
420 - qcom,sm6115-dwc3
421 - qcom,sm6125-dwc3
427 interrupt-names:
430 - const: dwc_usb3
431 - const: pwr_event
432 - const: qusb2_phy
433 - const: hs_phy_irq
434 - const: ss_phy_irq
436 - if:
441 - qcom,ipq5332-dwc3
446 interrupt-names:
448 - const: dwc_usb3
449 - const: pwr_event
450 - const: dp_hs_phy_irq
451 - const: dm_hs_phy_irq
453 - if:
458 - qcom,milos-dwc3
459 - qcom,x1e80100-dwc3
464 interrupt-names:
466 - const: dwc_usb3
467 - const: pwr_event
468 - const: dp_hs_phy_irq
469 - const: dm_hs_phy_irq
470 - const: ss_phy_irq
472 - if:
477 - qcom,ipq4019-dwc3
478 - qcom,ipq8064-dwc3
479 - qcom,msm8994-dwc3
480 - qcom,qcs615-dwc3
481 - qcom,qcs8300-dwc3
482 - qcom,qdu1000-dwc3
483 - qcom,sa8775p-dwc3
484 - qcom,sc7180-dwc3
485 - qcom,sc7280-dwc3
486 - qcom,sc8180x-dwc3
487 - qcom,sc8280xp-dwc3
488 - qcom,sdm670-dwc3
489 - qcom,sdm845-dwc3
490 - qcom,sdx55-dwc3
491 - qcom,sdx65-dwc3
492 - qcom,sdx75-dwc3
493 - qcom,sm4250-dwc3
494 - qcom,sm6350-dwc3
495 - qcom,sm8150-dwc3
496 - qcom,sm8250-dwc3
497 - qcom,sm8350-dwc3
498 - qcom,sm8450-dwc3
499 - qcom,sm8550-dwc3
500 - qcom,sm8650-dwc3
506 interrupt-names:
509 - const: dwc_usb3
510 - const: pwr_event
511 - const: hs_phy_irq
512 - const: dp_hs_phy_irq
513 - const: dm_hs_phy_irq
514 - const: ss_phy_irq
516 - if:
521 - qcom,sc8180x-dwc3-mp
522 - qcom,x1e80100-dwc3-mp
528 interrupt-names:
530 - const: dwc_usb3
531 - const: pwr_event_1
532 - const: pwr_event_2
533 - const: hs_phy_1
534 - const: hs_phy_2
535 - const: dp_hs_phy_1
536 - const: dm_hs_phy_1
537 - const: dp_hs_phy_2
538 - const: dm_hs_phy_2
539 - const: ss_phy_1
540 - const: ss_phy_2
542 - if:
547 - qcom,sc8280xp-dwc3-mp
553 interrupt-names:
555 - const: dwc_usb3
556 - const: pwr_event_1
557 - const: pwr_event_2
558 - const: pwr_event_3
559 - const: pwr_event_4
560 - const: hs_phy_1
561 - const: hs_phy_2
562 - const: hs_phy_3
563 - const: hs_phy_4
564 - const: dp_hs_phy_1
565 - const: dm_hs_phy_1
566 - const: dp_hs_phy_2
567 - const: dm_hs_phy_2
568 - const: dp_hs_phy_3
569 - const: dm_hs_phy_3
570 - const: dp_hs_phy_4
571 - const: dm_hs_phy_4
572 - const: ss_phy_1
573 - const: ss_phy_2
578 - |
579 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
580 #include <dt-bindings/interrupt-controller/arm-gic.h>
581 #include <dt-bindings/interrupt-controller/irq.h>
583 #address-cells = <2>;
584 #size-cells = <2>;
587 compatible = "qcom,sdm845-dwc3", "qcom,snps-dwc3";
595 clock-names = "cfg_noc",
601 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
603 assigned-clock-rates = <19200000>, <150000000>;
611 interrupt-names = "dwc_usb3", "pwr_event", "hs_phy_irq",
614 power-domains = <&gcc USB30_PRIM_GDSC>;
622 phy-names = "usb2-phy", "usb3-phy";