Lines Matching +full:pwm +full:- +full:offset

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Dilip Kota <eswara.kota@linux.intel.com>
15       - intel,rcu-lgm
16       - intel,rcu-xrx200
22   intel,global-reset:
23     description: Global reset register offset and bit offset.
24     $ref: /schemas/types.yaml#/definitions/uint32-array
26       - description: Register offset
27       - description: Register bit offset
31   "#reset-cells":
35       First cell is reset request register offset.
36       Second cell is bit offset in reset request register.
37       Third cell is bit offset in reset status register.
38       For LGM SoC, reset cell count is 2 as bit offset in
40       3 for legacy SoCs as bit offset differs.
43   - compatible
44   - reg
45   - intel,global-reset
46   - "#reset-cells"
51   - |
52     rcu0: reset-controller@e0000000 {
53         compatible = "intel,rcu-lgm";
55         intel,global-reset = <0x10 30>;
56         #reset-cells = <2>;
59     pwm: pwm@e0d00000 {
60         compatible = "intel,lgm-pwm";
63         #pwm-cells = <2>;