Lines Matching +full:uhs +full:-
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
14 possible slots or ports for multi-slot controllers.
17 "#address-cells":
22 "#size-cells":
29 broken-cd:
34 cd-gpios:
39 non-removable:
42 Non-removable slot (like eMMC); assume always present.
48 # low." Therefore, using the "cd-inverted" property means, that the
50 # inserted. Similar logic applies to the "wp-inverted" property.
53 # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or
55 # using *-inverted properties. GPIO polarity can also be specified
60 # respective *-inverted property results in a
61 # double-inversion and actually means the "normal" line polarity is
63 wp-inverted:
68 cd-inverted:
75 bus-width:
82 max-frequency:
85 - for eMMC, the maximum supported frequency is 200MHz,
86 - for SD/SDIO cards the SDR104 mode has a max supported
88 - some mmc host controllers do support a max frequency up to
96 max-sd-hs-hz:
99 High-Speed (HS) mode.
104 disable-wp:
107 When set, no physical write-protect line is present. This
109 dedicated write-protect detection logic. If a GPIO is always used
110 for the write-protect detection logic, it is sufficient to not
111 specify the wp-gpios property in the absence of a write-protect
114 wp-gpios:
117 GPIO to use for the write-protect detection.
119 cd-debounce-delay-ms:
124 no-1-8-v:
130 cap-sd-highspeed:
133 SD high-speed timing is supported.
135 cap-mmc-highspeed:
138 MMC high-speed timing is supported.
140 sd-uhs-sdr12:
143 SD UHS SDR12 speed is supported.
145 sd-uhs-sdr25:
148 SD UHS SDR25 speed is supported.
150 sd-uhs-sdr50:
153 SD UHS SDR50 speed is supported.
155 sd-uhs-sdr104:
158 SD UHS SDR104 speed is supported.
160 sd-uhs-ddr50:
163 SD UHS DDR50 speed is supported.
165 cap-power-off-card:
170 cap-mmc-hw-reset:
175 cap-sdio-irq:
180 full-pwr-cycle:
185 full-pwr-cycle-in-suspend:
190 mmc-ddr-1_2v:
193 eMMC high-speed DDR mode (1.2V I/O) is supported.
195 mmc-ddr-1_8v:
198 eMMC high-speed DDR mode (1.8V I/O) is supported.
200 mmc-ddr-3_3v:
203 eMMC high-speed DDR mode (3.3V I/O) is supported.
205 mmc-hs200-1_2v:
210 mmc-hs200-1_8v:
215 mmc-hs400-1_2v:
220 mmc-hs400-1_8v:
225 mmc-hs400-enhanced-strobe:
230 no-mmc-hs400:
243 no-sdio:
249 no-sd:
254 no-mmc:
260 fixed-emmc-driver-type:
262 For non-removable eMMC, enforce this driver type. The value is
269 post-power-on-delay-ms:
271 It was invented for MMC pwrseq-simple which could be referred to
272 mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay
274 regardless of whether pwrseq-simple is used. Default to 10ms if
278 supports-cqe:
284 disable-cqe-dcmd:
291 keep-power-in-suspend:
296 wakeup-source:
301 vmmc-supply:
305 vqmmc-supply:
309 be modeled as a "regulator-fixed" with a GPIO line for
312 mmc-pwrseq:
315 System-on-Chip designs may specify a specific MMC power
320 "^.*@[0-9]+$":
338 - minimum: 0
346 - reg
348 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
349 $ref: /schemas/types.yaml#/definitions/uint32-array
362 cd-debounce-delay-ms: [ cd-gpios ]
363 fixed-emmc-driver-type: [ non-removable ]