Lines Matching +full:num +full:- +full:irq +full:- +full:priority +full:- +full:bits

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,nvic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Rob Herring <robh@kernel.org>
13   The NVIC provides an interrupt controller that is tightly coupled to Cortex-M
15   number of interrupts and priority bits per interrupt.
20       - arm,armv7m-nvic # deprecated
21       - arm,v6m-nvic
22       - arm,v7m-nvic
23       - arm,v8m-nvic
28   '#address-cells':
31   interrupt-controller: true
33   '#interrupt-cells':
37       first = interrupt number, second = priority.
39   arm,num-irq-priority-bits:
40     description: Number of priority bits implemented by the SoC
45   - compatible
46   - reg
47   - interrupt-controller
48   - '#interrupt-cells'
49   - arm,num-irq-priority-bits
54   - |
55     interrupt-controller@e000e100 {
56         compatible = "arm,v7m-nvic";
57         #interrupt-cells = <2>;
58         #address-cells = <0>;
59         interrupt-controller;
61         arm,num-irq-priority-bits = <4>;