Lines Matching +full:dsp +full:- +full:irq

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/ti,keystone-dsp-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Keystone 2 DSP GPIO controller
10   - Grygorii Strashko <grygorii.strashko@ti.com>
13   HOST OS userland running on ARM can send interrupts to DSP cores using
14   the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
17   For example TCI6638K2K SoC has 8 DSP GPIO controllers:
18    - 8 for C66x CorePacx CPUs 0-7
20   Keystone 2 DSP GPIO controller has specific features:
21   - each GPIO can be configured only as output pin;
22   - setting GPIO value to 1 causes IRQ generation on target DSP core;
23   - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
28     const: ti,keystone-dsp-gpio
33   gpio-controller: true
35   '#gpio-cells':
38   gpio,syscon-dev:
42     $ref: /schemas/types.yaml#/definitions/phandle-array
44       - items:
45           - description: phandle to syscon
46           - description: register offset within state control registers
49   - compatible
50   - reg
51   - gpio-controller
52   - '#gpio-cells'
53   - gpio,syscon-dev
58   - |
60         compatible = "ti,keystone-dsp-gpio";
62         gpio-controller;
63         #gpio-cells = <2>;
64         gpio,syscon-dev = <&devctrl 0x240>;