Lines Matching +full:dsi +full:- +full:to +full:- +full:edp
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 series of SoCs which transfers the image data from a video memory buffer to
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <heiko@sntech.de>
21 - rockchip,rk3566-vop
22 - rockchip,rk3568-vop
23 - rockchip,rk3588-vop
27 - description:
28 Must contain one entry corresponding to the base address and length
30 - description:
31 Can optionally contain a second entry corresponding to the CRTC gamma
34 reg-names:
36 - const: vop
37 - const: gamma-lut
45 # See compatible-specific constraints below.
49 - description: Clock for ddr buffer transfer via axi.
50 - description: Clock for the ahb bus to R/W the regs.
51 - description: Pixel clock for video port 0.
52 - description: Pixel clock for video port 1.
53 - description: Pixel clock for video port 2.
54 - description: Pixel clock for video port 3.
55 - description: Peripheral(vop grf/dsi) clock.
57 clock-names:
60 - const: aclk
61 - const: hclk
62 - const: dclk_vp0
63 - const: dclk_vp1
64 - const: dclk_vp2
65 - const: dclk_vp3
66 - const: pclk_vop
71 Phandle to GRF regs used for control the polarity of dclk/hsync/vsync of DPI,
74 rockchip,vo1-grf:
77 Phandle to VO GRF regs used for control the polarity of dclk/hsync/vsync of hdmi
80 rockchip,vop-grf:
83 Phandle to VOP GRF regs used for control data path between vopr and hdmi/edp.
88 Phandle to PMU GRF used for query vop memory bisr status on rk3588.
94 "^port@[0-3]$":
99 - port@0
106 power-domains:
110 - compatible
111 - reg
112 - reg-names
113 - interrupts
114 - clocks
115 - clock-names
116 - ports
119 - if:
123 const: rockchip,rk3588-vop
128 clock-names:
133 - port@0
134 - port@1
135 - port@2
136 - port@3
139 - rockchip,grf
140 - rockchip,vo1-grf
141 - rockchip,vop-grf
142 - rockchip,pmu
146 rockchip,vo1-grf: false
147 rockchip,vop-grf: false
152 clock-names:
157 - port@0
158 - port@1
159 - port@2
164 - |
165 #include <dt-bindings/clock/rk3568-cru.h>
166 #include <dt-bindings/interrupt-controller/arm-gic.h>
167 #include <dt-bindings/power/rk3568-power.h>
169 #address-cells = <2>;
170 #size-cells = <2>;
172 compatible = "rockchip,rk3568-vop";
174 reg-names = "vop", "gamma-lut";
181 clock-names = "aclk",
186 power-domains = <&power RK3568_PD_VO>;
189 #address-cells = <1>;
190 #size-cells = <0>;
193 #address-cells = <1>;
194 #size-cells = <0>;
198 #address-cells = <1>;
199 #size-cells = <0>;
203 #address-cells = <1>;
204 #size-cells = <0>;