Lines Matching +full:x1e80100 +full:- +full:dpu
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-dpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8650 Display DPU
10 - Neil Armstrong <neil.armstrong@linaro.org>
12 $ref: /schemas/display/msm/dpu-common.yaml#
17 - qcom,sm8650-dpu
18 - qcom,x1e80100-dpu
22 - description: Address offset and size for mdp register set
23 - description: Address offset and size for vbif register set
25 reg-names:
27 - const: mdp
28 - const: vbif
32 - description: Display hf axi
33 - description: Display MDSS ahb
34 - description: Display lut
35 - description: Display core
36 - description: Display vsync
38 clock-names:
40 - const: nrt_bus
41 - const: iface
42 - const: lut
43 - const: core
44 - const: vsync
47 - compatible
48 - reg
49 - reg-names
50 - clocks
51 - clock-names
56 - |
57 #include <dt-bindings/interrupt-controller/arm-gic.h>
58 #include <dt-bindings/power/qcom,rpmhpd.h>
60 display-controller@ae01000 {
61 compatible = "qcom,sm8650-dpu";
64 reg-names = "mdp", "vbif";
71 clock-names = "nrt_bus",
77 assigned-clocks = <&dispcc_vsync_clk>;
78 assigned-clock-rates = <19200000>;
80 operating-points-v2 = <&mdp_opp_table>;
81 power-domains = <&rpmhpd RPMHPD_MMCX>;
83 interrupt-parent = <&mdss>;
87 #address-cells = <1>;
88 #size-cells = <0>;
93 remote-endpoint = <&dsi0_in>;
100 remote-endpoint = <&dsi1_in>;
105 mdp_opp_table: opp-table {
106 compatible = "operating-points-v2";
108 opp-200000000 {
109 opp-hz = /bits/ 64 <200000000>;
110 required-opps = <&rpmhpd_opp_low_svs>;
113 opp-325000000 {
114 opp-hz = /bits/ 64 <325000000>;
115 required-opps = <&rpmhpd_opp_svs>;
118 opp-375000000 {
119 opp-hz = /bits/ 64 <375000000>;
120 required-opps = <&rpmhpd_opp_svs_l1>;
123 opp-514000000 {
124 opp-hz = /bits/ 64 <514000000>;
125 required-opps = <&rpmhpd_opp_nom>;