Lines Matching +full:displayport +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mahadevan <quic_mahap@quicinc.com>
13 SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DP interfaces and EDP etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sa8775p-mdss
24 - description: Display AHB
25 - description: Display hf AXI
26 - description: Display core
34 interconnect-names:
38 "^display-controller@[0-9a-f]+$":
44 const: qcom,sa8775p-dpu
46 "^displayport-controller@[0-9a-f]+$":
53 - const: qcom,sa8775p-dp
55 "^dsi@[0-9a-f]+$":
61 const: qcom,sa8775p-dsi-ctrl
63 "^phy@[0-9a-f]+$":
70 - qcom,sa8775p-dsi-phy-5nm
71 - qcom,sa8775p-edp-phy
74 - compatible
79 - |
80 #include <dt-bindings/interconnect/qcom,icc.h>
81 #include <dt-bindings/interrupt-controller/arm-gic.h>
82 #include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
83 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
84 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
85 #include <dt-bindings/power/qcom,rpmhpd.h>
86 #include <dt-bindings/power/qcom-rpmpd.h>
88 display-subsystem@ae00000 {
89 compatible = "qcom,sa8775p-mdss";
91 reg-names = "mdss";
96 interconnect-names = "mdp0-mem",
97 "mdp1-mem",
98 "cpu-cfg";
101 power-domains = <&dispcc_gdsc>;
108 interrupt-controller;
109 #interrupt-cells = <1>;
113 #address-cells = <1>;
114 #size-cells = <1>;
117 display-controller@ae01000 {
118 compatible = "qcom,sa8775p-dpu";
121 reg-names = "mdp", "vbif";
128 clock-names = "nrt_bus",
134 assigned-clocks = <&dispcc_mdp_vsync_clk>;
135 assigned-clock-rates = <19200000>;
137 operating-points-v2 = <&mdss0_mdp_opp_table>;
138 power-domains = <&rpmhpd RPMHPD_MMCX>;
140 interrupt-parent = <&mdss0>;
144 #address-cells = <1>;
145 #size-cells = <0>;
150 remote-endpoint = <&mdss0_dp0_in>;
157 remote-endpoint = <&mdss0_dsi0_in>;
164 remote-endpoint = <&mdss0_dsi1_in>;
169 mdss0_mdp_opp_table: opp-table {
170 compatible = "operating-points-v2";
172 opp-375000000 {
173 opp-hz = /bits/ 64 <375000000>;
174 required-opps = <&rpmhpd_opp_svs_l1>;
177 opp-500000000 {
178 opp-hz = /bits/ 64 <500000000>;
179 required-opps = <&rpmhpd_opp_nom>;
182 opp-575000000 {
183 opp-hz = /bits/ 64 <575000000>;
184 required-opps = <&rpmhpd_opp_turbo>;
187 opp-650000000 {
188 opp-hz = /bits/ 64 <650000000>;
189 required-opps = <&rpmhpd_opp_turbo_l1>;
195 compatible = "qcom,sa8775p-edp-phy";
204 clock-names = "aux",
207 #clock-cells = <1>;
208 #phy-cells = <0>;
210 vdda-phy-supply = <&vreg_l1c>;
211 vdda-pll-supply = <&vreg_l4a>;
215 compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl";
217 reg-names = "dsi_ctrl";
219 interrupt-parent = <&mdss>;
228 clock-names = "byte",
234 assigned-clocks = <&dispcc_byte_clk>,
236 assigned-clock-parents = <&mdss0_dsi0_phy 0>, <&mdss0_dsi0_phy 1>;
239 operating-points-v2 = <&dsi0_opp_table>;
240 power-domains = <&rpmhpd SA8775P_MMCX>;
242 #address-cells = <1>;
243 #size-cells = <0>;
246 #address-cells = <1>;
247 #size-cells = <0>;
252 remote-endpoint = <&dpu_intf1_out>;
262 dsi0_opp_table: opp-table {
263 compatible = "operating-points-v2";
265 opp-358000000 {
266 opp-hz = /bits/ 64 <358000000>;
267 required-opps = <&rpmhpd_opp_svs_l1>;
273 compatible = "qcom,sa8775p-dsi-phy-5nm";
277 reg-names = "dsi_phy",
281 #clock-cells = <1>;
282 #phy-cells = <0>;
286 clock-names = "iface", "ref";
288 vdds-supply = <&vreg_dsi_supply>;
292 compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl";
294 reg-names = "dsi_ctrl";
296 interrupt-parent = <&mdss>;
305 clock-names = "byte",
311 assigned-clocks = <&dispcc_byte_clk>,
313 assigned-clock-parents = <&mdss0_dsi1_phy 0>, <&mdss0_dsi1_phy 1>;
316 operating-points-v2 = <&dsi1_opp_table>;
317 power-domains = <&rpmhpd SA8775P_MMCX>;
319 #address-cells = <1>;
320 #size-cells = <0>;
323 #address-cells = <1>;
324 #size-cells = <0>;
329 remote-endpoint = <&dpu_intf2_out>;
339 dsi1_opp_table: opp-table {
340 compatible = "operating-points-v2";
342 opp-358000000 {
343 opp-hz = /bits/ 64 <358000000>;
344 required-opps = <&rpmhpd_opp_svs_l1>;
350 compatible = "qcom,sa8775p-dsi-phy-5nm";
354 reg-names = "dsi_phy",
358 #clock-cells = <1>;
359 #phy-cells = <0>;
363 clock-names = "iface", "ref";
365 vdds-supply = <&vreg_dsi_supply>;
368 displayport-controller@af54000 {
369 compatible = "qcom,sa8775p-dp";
371 pinctrl-0 = <&dp_hot_plug_det>;
372 pinctrl-names = "default";
380 interrupt-parent = <&mdss0>;
388 clock-names = "core_iface",
394 assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
396 assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
399 phy-names = "dp";
401 operating-points-v2 = <&dp_opp_table>;
402 power-domains = <&rpmhpd SA8775P_MMCX>;
404 #sound-dai-cells = <0>;
407 #address-cells = <1>;
408 #size-cells = <0>;
413 remote-endpoint = <&dpu_intf0_out>;
423 dp_opp_table: opp-table {
424 compatible = "operating-points-v2";
426 opp-160000000 {
427 opp-hz = /bits/ 64 <160000000>;
428 required-opps = <&rpmhpd_opp_low_svs>;
431 opp-270000000 {
432 opp-hz = /bits/ 64 <270000000>;
433 required-opps = <&rpmhpd_opp_svs>;
436 opp-540000000 {
437 opp-hz = /bits/ 64 <540000000>;
438 required-opps = <&rpmhpd_opp_svs_l1>;
441 opp-810000000 {
442 opp-hz = /bits/ 64 <810000000>;
443 required-opps = <&rpmhpd_opp_nom>;