Lines Matching +full:gcc +full:- +full:ipq5424
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IPQ5424
10 - Bjorn Andersson <andersson@kernel.org>
11 - Anusha Rao <quic_anusha@quicinc.com>
15 resets on IPQ9574 and IPQ5424
18 include/dt-bindings/clock/qcom,ipq5424-nsscc.h
19 include/dt-bindings/clock/qcom,ipq9574-nsscc.h
20 include/dt-bindings/reset/qcom,ipq5424-nsscc.h
21 include/dt-bindings/reset/qcom,ipq9574-nsscc.h
26 - qcom,ipq5424-nsscc
27 - qcom,ipq9574-nsscc
31 - description: Board XO source
32 - description: CMN_PLL NSS (Bias PLL cc) clock source. This clock rate
34 IPQ9574 and 300 MHz on the IPQ5424.
35 - description: CMN_PLL PPE (Bias PLL ubi nc) clock source. The clock
37 on the IPQ9574 and 375 MHz on the IPQ5424.
38 - description: GCC GPLL0 OUT AUX clock source
39 - description: Uniphy0 NSS Rx clock source
40 - description: Uniphy0 NSS Tx clock source
41 - description: Uniphy1 NSS Rx clock source
42 - description: Uniphy1 NSS Tx clock source
43 - description: Uniphy2 NSS Rx clock source
44 - description: Uniphy2 NSS Tx clock source
45 - description: GCC NSSCC clock source
47 '#interconnect-cells':
50 clock-names:
52 - const: xo
53 - enum:
54 - nss_1200
55 - nss
56 - enum:
57 - ppe_353
58 - ppe
59 - const: gpll0_out
60 - const: uniphy0_rx
61 - const: uniphy0_tx
62 - const: uniphy1_rx
63 - const: uniphy1_tx
64 - const: uniphy2_rx
65 - const: uniphy2_tx
66 - const: bus
69 - compatible
70 - clocks
71 - clock-names
74 - $ref: qcom,gcc.yaml#
75 - if:
78 const: qcom,ipq9574-nsscc
81 clock-names:
83 - const: xo
84 - const: nss_1200
85 - const: ppe_353
86 - const: gpll0_out
87 - const: uniphy0_rx
88 - const: uniphy0_tx
89 - const: uniphy1_rx
90 - const: uniphy1_tx
91 - const: uniphy2_rx
92 - const: uniphy2_tx
93 - const: bus
96 clock-names:
98 - const: xo
99 - const: nss
100 - const: ppe
101 - const: gpll0_out
102 - const: uniphy0_rx
103 - const: uniphy0_tx
104 - const: uniphy1_rx
105 - const: uniphy1_tx
106 - const: uniphy2_rx
107 - const: uniphy2_tx
108 - const: bus
113 - |
114 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
115 #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
116 clock-controller@39b00000 {
117 compatible = "qcom,ipq9574-nsscc";
122 <&gcc GPLL0_OUT_AUX>,
129 <&gcc GCC_NSSCC_CLK>;
130 clock-names = "xo",
141 #clock-cells = <1>;
142 #reset-cells = <1>;
143 #interconnect-cells = <1>;