| 900b32fd | 25-Nov-2025 |
Hal Feng <hal.feng@starfivetech.com> |
riscv: dts: starfive: Add VisionFive 2 Lite board device tree
VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S SoC.
Board features: - JH7110S SoC - 4/8 GiB LPDDR4 DRAM - AXP15060 PMIC
riscv: dts: starfive: Add VisionFive 2 Lite board device tree
VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S SoC.
Board features: - JH7110S SoC - 4/8 GiB LPDDR4 DRAM - AXP15060 PMIC - 40 pin GPIO header - 1x USB 3.0 host port - 3x USB 2.0 host port - 1x M.2 M-Key (size: 2242) - 1x MicroSD slot (optional non-removable 64GiB eMMC) - 1x QSPI Flash - 1x I2C EEPROM - 1x 1Gbps Ethernet port - SDIO-based Wi-Fi & UART-based Bluetooth - 1x HDMI port - 1x 2-lane DSI - 1x 2-lane CSI
VisionFive 2 Lite schematics: https://doc-en.rvspace.org/VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/VisionFive2Lite/VisionFive2LiteQSG/index.html More documents: https://doc-en.rvspace.org/Doc_Center/visionfive_2_lite.html
Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Tested-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 2ad6d71a | 25-Nov-2025 |
Hal Feng <hal.feng@starfivetech.com> |
riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants
Add a common board dtsi for use by VisionFive 2 Lite and VisionFive 2 Lite eMMC.
Acked-by: Emil Renner Berthing <emil.renn
riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants
Add a common board dtsi for use by VisionFive 2 Lite and VisionFive 2 Lite eMMC.
Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Tested-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 4cce8b25 | 05-Sep-2025 |
E Shattow <e@freeshell.de> |
riscv: dts: starfive: add Milk-V Mars CM Lite system-on-module
Milk-V Mars CM Lite is a System-on-Module based on the Milk-V Mars CM without the onboard eMMC storage component populated and configur
riscv: dts: starfive: add Milk-V Mars CM Lite system-on-module
Milk-V Mars CM Lite is a System-on-Module based on the Milk-V Mars CM without the onboard eMMC storage component populated and configured instead for SD3.0 Card Slot on that interface via 100-pin connector.
Link to Milk-V Mars CM Lite schematics: https://github.com/milkv-mars/mars-files/tree/main/Mars-CM_Hardware_Schematices Link to StarFive JH7110 Technical Reference Manual: https://doc-en.rvspace.org/JH7110/TRM/index.html Link to Raspberry Pi CM4IO datasheet: https://datasheets.raspberrypi.com/cm4io/cm4io-datasheet.pdf
Add the devicetree file to make use of StarFive JH7110 common supported features PMIC, EEPROM, UART, I2C, GPIO, PCIe, QSPI Flash, PWM, and Ethernet. Also configure the eMMC interface mmc0 for SD Card use and configure the common SD Card interface mmc1 for onboard SDIO BT+WiFi.
Signed-off-by: E Shattow <e@freeshell.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 8d193bc0 | 05-Sep-2025 |
E Shattow <e@freeshell.de> |
riscv: dts: starfive: add Milk-V Mars CM system-on-module
Milk-V Mars CM is a System-on-Module based on the StarFive VisionFive 2 board and Radxa CM3 System-on-Module compatible with the Raspberry P
riscv: dts: starfive: add Milk-V Mars CM system-on-module
Milk-V Mars CM is a System-on-Module based on the StarFive VisionFive 2 board and Radxa CM3 System-on-Module compatible with the Raspberry Pi CM4IO Classic IO Board.
Mars CM SoM features:
- StarFive JH7110 System on Chip with RV64GC up to 1.5GHz - AXP15060 Power Management Unit - LPDDR4 2GB / 4GB / 8GB DRAM memory - BL24C04F 4K bits (512 x 8) EEPROM - GigaDevice 25LQ128EWIG QSPI NOR Flash 16M or SoC ROM UART loader for boot (selectable by GPIO) - eMMC5.0 8GB / 16GB / 32GB flash storage onboard - AP6256 via SDIO 2.0 onboard wireless connectivity WiFi 5 + Bluetooth 5.2 (optional, present in models with WiFi feature) - 1x Motorcomm YT8531C Gigabit Ethernet PHY - IMG BXE-4-32 Integrated GPU with 3D Acceleration: - H.264 & H.265 4K@60fps Decoding - H.265 1080p@30fps Encoding - JPEG encoder / decoder
Additional features available via 2x 100-pin connectors for CM4IO Board: - 1x HDMI 2.0 - 1x MIPI DSI (4-lanes) - 1x 2CH Audio out (via GPIO) - 1x MIPI CSI (2x2-lanes or 1x4-lanes) - 1x USB 2.0 - 1x PCIe 1-lane Host, Gen 2 (5Gbps) - Up to 28x GPIO, supporting 3.3V - UART x6 - PWM x8 - I2C x7 - SPI - I2S
Link to Milk-V Mars CM schematics: https://github.com/milkv-mars/mars-files/tree/main/Mars-CM_Hardware_Schematices Link to StarFive JH7110 Technical Reference Manual: https://doc-en.rvspace.org/JH7110/TRM/index.html Link to Raspberry Pi CM4IO datasheet: https://datasheets.raspberrypi.com/cm4io/cm4io-datasheet.pdf
Add the devicetree file to make use of StarFive JH7110 common supported features PMIC, EEPROM, UART, I2C, GPIO, eMMC, PCIe, QSPI Flash, PWM, and Ethernet. Also configure the common SD Card interface mmc1 for onboard SDIO BT+WiFi.
Signed-off-by: E Shattow <e@freeshell.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| b5a861a4 | 03-Sep-2025 |
E Shattow <e@freeshell.de> |
riscv: dts: starfive: jh7110-common: drop mmc post-power-on-delay-ms
Drop post-power-on-delay-ms from mmc0 mmc1 interfaces. There is no known reason for these properties to continue, testing appears
riscv: dts: starfive: jh7110-common: drop mmc post-power-on-delay-ms
Drop post-power-on-delay-ms from mmc0 mmc1 interfaces. There is no known reason for these properties to continue, testing appears to be fine without them [1].
1: https://lore.kernel.org/lkml/NT0PR01MB1312E0D9EE9F158A57B77700E63D2@NT0PR01MB1312.CHNPR01.prod.partner.outlook.cn/
Signed-off-by: E Shattow <e@freeshell.de> Tested-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 08128670 | 03-Sep-2025 |
E Shattow <e@freeshell.de> |
riscv: dts: starfive: jh7110-common: drop no-mmc property from mmc1
Relax no-mmc restriction on mmc1 for jh7110 boards. The restriction is only needed to block use of commands that would cause a dev
riscv: dts: starfive: jh7110-common: drop no-mmc property from mmc1
Relax no-mmc restriction on mmc1 for jh7110 boards. The restriction is only needed to block use of commands that would cause a device to malfunction, which by testing and observation [1] is not any problem.
1: https://lore.kernel.org/lkml/NT0PR01MB1312E0D9EE9F158A57B77700E63D2@NT0PR01MB1312.CHNPR01.prod.partner.outlook.cn/
Signed-off-by: E Shattow <e@freeshell.de> Tested-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 8181cc2f | 23-Aug-2025 |
E Shattow <e@freeshell.de> |
riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader
Add bootph-pre-ram hinting to jh7110.dtsi: - CPU interrupt controller(s) - gmac1_rgmii_rxin fixed-clock (dependency of
riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader
Add bootph-pre-ram hinting to jh7110.dtsi: - CPU interrupt controller(s) - gmac1_rgmii_rxin fixed-clock (dependency of syscrg) - gmac1_rmii_refin fixed-clock (dependency of syscrg) - oscillator - core local interrupt timer - syscrg clock-controller - pllclk clock-controller (dependency of syscrg) - DDR memory controller
Signed-off-by: E Shattow <e@freeshell.de> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 71149690 | 23-Aug-2025 |
E Shattow <e@freeshell.de> |
riscv: dts: starfive: jh7110: add DMC memory controller
Add JH7110 SoC DDR external memory controller.
Signed-off-by: E Shattow <e@freeshell.de> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Re
riscv: dts: starfive: jh7110: add DMC memory controller
Add JH7110 SoC DDR external memory controller.
Signed-off-by: E Shattow <e@freeshell.de> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| d5010870 | 02-May-2025 |
E Shattow <e@freeshell.de> |
riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader
Add bootph-pre-ram hinting to jh7110-common.dtsi: - i2c5_pins and i2c-pins subnode for connection to eeprom - ee
riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader
Add bootph-pre-ram hinting to jh7110-common.dtsi: - i2c5_pins and i2c-pins subnode for connection to eeprom - eeprom node - qspi flash configuration subnode - memory node - mmc0 for eMMC - mmc1 for SD Card - uart0 for serial console
With this the U-Boot SPL secondary program loader may drop such overrides.
Signed-off-by: E Shattow <e@freeshell.de> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 63591811 | 02-May-2025 |
E Shattow <e@freeshell.de> |
riscv: dts: starfive: jh7110-common: add eeprom node to i2c5
StarFive VisionFive2 and similar JH7110 boards have an eeprom compatible with Atmel 24c04. Add the node so this may be used with the at24
riscv: dts: starfive: jh7110-common: add eeprom node to i2c5
StarFive VisionFive2 and similar JH7110 boards have an eeprom compatible with Atmel 24c04. Add the node so this may be used with the at24 driver.
Signed-off-by: E Shattow <e@freeshell.de> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 59404dce | 02-May-2025 |
E Shattow <e@freeshell.de> |
riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2 cycles max 100MHz
Use qspi flash read-delay and spi-max-frequency settings compatible with U-Boot bootloader.
Observations from
riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2 cycles max 100MHz
Use qspi flash read-delay and spi-max-frequency settings compatible with U-Boot bootloader.
Observations from testing on Pine64 Star64 hardware within U-Boot bootloader and read-delay=2 are spi-max-frequency less than 49.8MHz fails to write, corrupt data writes at 25MHz to 49.799999MHz, and valid data writes at 49.8MHz to 100MHz (not tested above 100MHz). No valid spi-max-frequency was found for 1<read-delay<=3 and corrupt data with read-delay=3.
Looking around the Linux codebase it is common to see read-delay 2 cycles with spi-max-frequency 100MHz and testing confirms this to work in both U-Boot and Linux.
Signed-off-by: E Shattow <e@freeshell.de> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 724a6718 | 02-May-2025 |
E Shattow <e@freeshell.de> |
riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg
Add syscrg clock assignments for CPU, BUS, PERH, and QSPI as required by boot loader before kernel.
Signed-off-by: E Shat
riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg
Add syscrg clock assignments for CPU, BUS, PERH, and QSPI as required by boot loader before kernel.
Signed-off-by: E Shattow <e@freeshell.de> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 71385a89 | 24-Apr-2025 |
Icenowy Zheng <uwu@icenowy.me> |
riscv: dts: starfive: jh7110-common: use macros for MMC0 pins
The pin names of MMC0 pinmux is defined in the pinctrl dt binding header associated with starfive,jh7110-pinctrl .
Include the header f
riscv: dts: starfive: jh7110-common: use macros for MMC0 pins
The pin names of MMC0 pinmux is defined in the pinctrl dt binding header associated with starfive,jh7110-pinctrl .
Include the header file and use these names instead of raw numbers for defining MMC0 pinmux.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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