| d5010870 | 02-May-2025 |
E Shattow <e@freeshell.de> |
riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader
Add bootph-pre-ram hinting to jh7110-common.dtsi:
- i2c5_pins and i2c-pins subnode for connection to eeprom
- ee
riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader
Add bootph-pre-ram hinting to jh7110-common.dtsi:
- i2c5_pins and i2c-pins subnode for connection to eeprom
- eeprom node
- qspi flash configuration subnode
- memory node
- mmc0 for eMMC
- mmc1 for SD Card
- uart0 for serial console
With this the U-Boot SPL secondary program loader may drop such overrides.
Signed-off-by: E Shattow <e@freeshell.de>
Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 63591811 | 02-May-2025 |
E Shattow <e@freeshell.de> |
riscv: dts: starfive: jh7110-common: add eeprom node to i2c5
StarFive VisionFive2 and similar JH7110 boards have an eeprom compatible
with Atmel 24c04. Add the node so this may be used with the at24
riscv: dts: starfive: jh7110-common: add eeprom node to i2c5
StarFive VisionFive2 and similar JH7110 boards have an eeprom compatible
with Atmel 24c04. Add the node so this may be used with the at24 driver.
Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 59404dce | 02-May-2025 |
E Shattow <e@freeshell.de> |
riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2 cycles max 100MHz
Use qspi flash read-delay and spi-max-frequency settings compatible with
U-Boot bootloader.
Observations from
riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2 cycles max 100MHz
Use qspi flash read-delay and spi-max-frequency settings compatible with
U-Boot bootloader.
Observations from testing on Pine64 Star64 hardware within U-Boot bootloader
and read-delay=2 are spi-max-frequency less than 49.8MHz fails to write,
corrupt data writes at 25MHz to 49.799999MHz, and valid data writes at
49.8MHz to 100MHz (not tested above 100MHz). No valid spi-max-frequency
was found for 1<read-delay<=3 and corrupt data with read-delay=3.
Looking around the Linux codebase it is common to see read-delay 2 cycles
with spi-max-frequency 100MHz and testing confirms this to work in both
U-Boot and Linux.
Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 724a6718 | 02-May-2025 |
E Shattow <e@freeshell.de> |
riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg
Add syscrg clock assignments for CPU, BUS, PERH, and QSPI as required by
boot loader before kernel.
Signed-off-by: E Shat
riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg
Add syscrg clock assignments for CPU, BUS, PERH, and QSPI as required by
boot loader before kernel.
Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 71385a89 | 24-Apr-2025 |
Icenowy Zheng <uwu@icenowy.me> |
riscv: dts: starfive: jh7110-common: use macros for MMC0 pins
The pin names of MMC0 pinmux is defined in the pinctrl dt binding header
associated with starfive,jh7110-pinctrl .
Include the header f
riscv: dts: starfive: jh7110-common: use macros for MMC0 pins
The pin names of MMC0 pinmux is defined in the pinctrl dt binding header
associated with starfive,jh7110-pinctrl .
Include the header file and use these names instead of raw numbers for
defining MMC0 pinmux.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 38818f7c | 02-Jan-2025 |
E Shattow <e@freeshell.de> |
riscv: dts: starfive: jh7110-pine64-star64: enable USB 3.0 port
One of four USB-A ports on the Pine64 Star64 is USB 3.0 which requires to
disable PCIE0 and change the mode of PCIE0 PHY to USB3.0 ope
riscv: dts: starfive: jh7110-pine64-star64: enable USB 3.0 port
One of four USB-A ports on the Pine64 Star64 is USB 3.0 which requires to
disable PCIE0 and change the mode of PCIE0 PHY to USB3.0 operation. The
remaining three USB-A ports are USB 2.0 with the USB0 PHY and do not
conflict with any of PCIE0 or PCIE1. PCIE1 (1-lane) routes to a PCIe X4
connector.
Signed-off-by: E Shattow <e@freeshell.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 65e8b991 | 02-Jan-2025 |
E Shattow <e@freeshell.de> |
riscv: dts: starfive: jh7110: pciephy0 USB 3.0 configuration registers
StarFive JH7110 contains a Cadence USB2.0+USB3.0 controller IP block that
may exclusively use pciephy0 for USB3.0 connectivity.
riscv: dts: starfive: jh7110: pciephy0 USB 3.0 configuration registers
StarFive JH7110 contains a Cadence USB2.0+USB3.0 controller IP block that
may exclusively use pciephy0 for USB3.0 connectivity. Add the register
offsets for the driver to enable/disable USB3.0 on pciephy0.
Signed-off-by: E Shattow <e@freeshell.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 57b5369f | 07-Feb-2025 |
Sandie Cao <sandie.cao@deepcomputing.io> |
riscv: dts: starfive: fml13v01: enable pcie1
Starfive Soc common defines GPIO28 as pcie1 reset, GPIO21 as pcie1 wakeup;
But the FML13V01 board uses GPIO21 as pcie1 reset, GPIO28 as pcie1 wakeup;
red
riscv: dts: starfive: fml13v01: enable pcie1
Starfive Soc common defines GPIO28 as pcie1 reset, GPIO21 as pcie1 wakeup;
But the FML13V01 board uses GPIO21 as pcie1 reset, GPIO28 as pcie1 wakeup;
redefine pcie1 gpio and enable pcie1 for pcie based Wi-Fi.
Signed-off-by: Sandie Cao <sandie.cao@deepcomputing.io>
Tested-by: Maud Spierings <maud_spierings@hotmail.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 4bdea6e3 | 13-Feb-2025 |
Conor Dooley <conor.dooley@microchip.com> |
riscv: dts: starfive: remove non-existent dac from jh7110
The jh7110 boards do not have a Rohm DAC on them as far as I
can tell, and they certainly do not have a dh2228fv, as this device does
not ac
riscv: dts: starfive: remove non-existent dac from jh7110
The jh7110 boards do not have a Rohm DAC on them as far as I
can tell, and they certainly do not have a dh2228fv, as this device does
not actually exist! Remove the dac nodes from the devicetrees as it is
not acceptable to pretend to have a device on a board in order to bind
the spidev driver in Linux.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 708d55db | 27-Nov-2024 |
E Shattow <e@freeshell.de> |
riscv: dts: starfive: jh7110-milkv-mars: enable usb0 host function
Milk-V Mars board routes one of four USB-A ports to USB0 on the SoC
rather than to the VL805 USB 3.0 <-> PCIe chip.
Set JH7110 on-c
riscv: dts: starfive: jh7110-milkv-mars: enable usb0 host function
Milk-V Mars board routes one of four USB-A ports to USB0 on the SoC
rather than to the VL805 USB 3.0 <-> PCIe chip.
Set JH7110 on-chip USB host mode and vbus pin assignment accordingly.
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: E Shattow <e@freeshell.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| c8b72c30 | 28-Oct-2024 |
Sandie Cao <sandie.cao@deepcomputing.io> |
riscv: dts: starfive: add DeepComputing FML13V01 board device tree
The FML13V01 board from DeepComputing incorporates a StarFive JH7110 SoC.
It is a mainboard designed for the Framework Laptop 13 Ch
riscv: dts: starfive: add DeepComputing FML13V01 board device tree
The FML13V01 board from DeepComputing incorporates a StarFive JH7110 SoC.
It is a mainboard designed for the Framework Laptop 13 Chassis, which has
(Framework) SKU FRANHQ0001.
The FML13V01 board features:
- StarFive JH7110 SoC
- LPDDR4 8GB
- eMMC 32GB or 128GB
- QSPI Flash
- MicroSD Slot
- PCIe-based Wi-Fi
- 4 USB-C Ports
- Port 1: PD 3.0 (60W Max), USB 3.2 Gen 1, DP 1.4 (4K@30Hz/2.5K@60Hz)
- Port 2: PD 3.0 (60W Max), USB 3.2 Gen 1
- Port 3 & 4: USB 3.2 Gen 1
Create the DTS file for the DeepComputing FML13V01 board. Based on
'jh7110-common.dtsi', usb0 is enabled and is set to operate as a "host".
Signed-off-by: Sandie Cao <sandie.cao@deepcomputing.io>
[elder@riscstar.com: revised the description, updated some nodes]
Signed-off-by: Alex Elder <elder@riscstar.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 817eac16 | 28-Oct-2024 |
Guodong Xu <guodong@riscstar.com> |
riscv: dts: starfive: jh7110-common: move usb0 config to board dts
The JH7110 USB0 can operate as a dual-role USB device. Different
boards can have different configuration.
For all current boards
riscv: dts: starfive: jh7110-common: move usb0 config to board dts
The JH7110 USB0 can operate as a dual-role USB device. Different
boards can have different configuration.
For all current boards this device operates in peripheral mode, but
on a new board this operates in host mode. This property will no
longer be common, so define the "dr_mode" property in the board files
rather than in the common DTSI file.
Signed-off-by: Alex Elder <elder@riscstar.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
show more ...
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| 825bb692 | 22-Oct-2024 |
E Shattow <e@freeshell.de> |
riscv: dts: starfive: Update ethernet phy0 delay parameter values for Star64
Improve function of Star64 bottom network port phy0 with updated delay values.
Initial upstream patches supporting Star64
riscv: dts: starfive: Update ethernet phy0 delay parameter values for Star64
Improve function of Star64 bottom network port phy0 with updated delay values.
Initial upstream patches supporting Star64 use the same vendor board support
package parameters known to result in an unreliable bottom network port.
Success acquiring DHCP lease and no dropped packets to ping LAN address:
rx 900: tx 1500 1650 1800 1950
rx 750: tx 1650 1800 1950
rx 600: tx 1800 1950
rx 1050: tx 1650 1800 1950
rx 1200: tx 1500 1650 1800 1950
rx 1350: tx 1500 1650 1800 1950
rx 1500: tx 1500 1650 1800 1950
rx 1650: tx 1500 1650 1800 1950
rx 1800: tx 1500 1650 1800 1950
rx 1900: tx 1950
rx 1950: tx 1950
Failure acquiring DHCP lease or many dropped packets:
rx 450: tx 1500 1800 1950
rx 600: tx 1200 1350 1650
rx 750: tx 1350 1500
rx 900: tx 1200 1350
rx 1050: tx 1050 1200 1350 1500
rx 1200: tx 1350
rx 1350: tx 1350
rx 1500: tx 1200 1350
rx 1650: tx 1050 1200 1350
rx 1800: tx 1050 1200 1350
rx 1900: tx 1500 1650 1800
rx 1950: tx 1200 1350
Non-functional:
rx 0: tx 0 150 300 450 600 750 900 1050 1200 1350 1500 1650 1800 1950
rx 150: tx 0 150 300 450 600 750 900 1050 1200 1350 1500 1650 1800 1950
rx 300: tx 0 150 300 450 600 750 900 1050 1200 1350 1500 1650 1800 1950
rx 450: tx 0 150 300 450 600 750 900 1050 1200 1350 1650
rx 600: tx 0 150 300 450 600 750 900 1050
rx 750: tx 0 150 300 450 600 750 900 1050 1200
rx 900: tx 0 150 300 450 600 750 900 1050
rx 1050: tx 0 150 300 450 600 750 900
rx 1200: tx 0 150 300 450 600 750 900 1050 1200
rx 1350: tx 0 150 300 450 600 750 900 1050 1200
rx 1500: tx 0 150 300 450 600 750 900 1050
rx 1650: tx 0 150 300 450 600 750 900
rx 1800: tx 0 150 300 450 600 750 900
rx 1900: tx 0 150 300 450 600 750 900 1050 1200 1350
rx 1950: tx 0 150 300 450 600 750 900 1050
Selecting the median of all working rx delay values 1500 combined with tx delay
values 1500, 1650, 1800, and 1950 only the tx delay value of 1950 (default) is
reliable as tested in both Linux 6.11.2 and U-Boot v2024.10
Signed-off-by: E Shattow <e@freeshell.de>
CC: stable@vger.kernel.org
Fixes: 2606bf583b962 ("riscv: dts: starfive: add Star64 board devicetree")
Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
show more ...
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