arm64: dts: ti: k3-am62a-phycore-som: Reorder properties per DTS coding style

Reorder properties to comply with the DeviceTree coding style guidelines:
https://docs.kernel.org/devicetree/bindings/dt

arm64: dts: ti: k3-am62a-phycore-som: Reorder properties per DTS coding style

Reorder properties to comply with the DeviceTree coding style guidelines:
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20250305085537.3976579-5-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-am642-phyboard-electra: Reorder properties per DTS coding style

Reorder properties to comply with the DeviceTree coding style guidelines:
https://docs.kernel.org/devicetree/bindin

arm64: dts: ti: k3-am642-phyboard-electra: Reorder properties per DTS coding style

Reorder properties to comply with the DeviceTree coding style guidelines:
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20250305085537.3976579-4-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-am642-phyboard-electra: Add boot phase tags

The bootph-all and bootph-pre-ram tags were introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across differen

arm64: dts: ti: k3-am642-phyboard-electra: Add boot phase tags

The bootph-all and bootph-pre-ram tags were introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across different
boot phases.

Add boot phase tags to all required nodes to ensure boot support from
all sources, including UART, Ethernet, uSD card, eMMC, and OSPI NOR Flash.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20250305085537.3976579-3-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-am62a-phycore-som: Add boot phase tags

The bootph-all and bootph-pre-ram tags were introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across different
boo

arm64: dts: ti: k3-am62a-phycore-som: Add boot phase tags

The bootph-all and bootph-pre-ram tags were introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across different
boot phases.

Add boot phase tags to all required nodes to ensure boot support from
all sources, including UART, USB (DFU), Ethernet, uSD card, eMMC, and
OSPI NOR Flash.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20250305085537.3976579-2-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-am62x-phyboard-lyra: Add boot phase tags

The bootph-all and bootph-pre-ram tags were introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across different
b

arm64: dts: ti: k3-am62x-phyboard-lyra: Add boot phase tags

The bootph-all and bootph-pre-ram tags were introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across different
boot phases.

Add boot phase tags to all required nodes to ensure boot support from
all sources, including UART, USB (DFU), Ethernet, uSD card, eMMC, and
OSPI NOR Flash.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20250305085537.3976579-1-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-j722s-evm: Add camera peripherals

J722S EVM has four RPi camera connectors and dual MIPI Samtec CSI
connectors which bring out the 4 x CSI2RX instances and the I2C camera
control

arm64: dts: ti: k3-j722s-evm: Add camera peripherals

J722S EVM has four RPi camera connectors and dual MIPI Samtec CSI
connectors which bring out the 4 x CSI2RX instances and the I2C camera
control interfaces. Add the nodes for PCA9543 I2C switch and enable them.

J722S EVM schematics: https://www.ti.com/lit/pdf/sprujb5

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
Link: https://lore.kernel.org/r/20250218185452.600797-4-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-j722s-main: Add CSI2RX nodes

J722S has 4 CSI2RX receiver instances with external DPHY. The first CSI2RX
instance node is derived from the AM62P common dtsi, Add the nodes for the

arm64: dts: ti: k3-j722s-main: Add CSI2RX nodes

J722S has 4 CSI2RX receiver instances with external DPHY. The first CSI2RX
instance node is derived from the AM62P common dtsi, Add the nodes for the
subsequent three instances and keep them disabled.

TRM (12.6 Camera Peripherals): https://www.ti.com/lit/zip/sprujb3

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
Link: https://lore.kernel.org/r/20250218185452.600797-3-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-j722s-main: Add BCDMA CSI overrides

J722S has a dedicated CSI BCDMA instance which is slightly different
from AM62P in TX channel support, add the overrides and additional
propert

arm64: dts: ti: k3-j722s-main: Add BCDMA CSI overrides

J722S has a dedicated CSI BCDMA instance which is slightly different
from AM62P in TX channel support, add the overrides and additional
properties to support CSI BCDMA on J722S.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
Link: https://lore.kernel.org/r/20250218185452.600797-2-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-j722s: fix pinctrl settings

It appears that pinctrl-single is misused on this SoC to control both
the mux and the input and output and bias settings. This results in
non-working p

arm64: dts: ti: k3-j722s: fix pinctrl settings

It appears that pinctrl-single is misused on this SoC to control both
the mux and the input and output and bias settings. This results in
non-working pinctrl configurations for GPIOs within the device tree.

This is what happens:
(1) During startup the pinctrl settings are applied according to the
device tree. I.e. the pin is configured as output and with
pull-ups enabled.
(2) During startup a device driver requests a GPIO.
(3) pinctrl-single is applying the default GPIO setting according to
the pinctrl-single,gpio-range property.

This would work as expected if the pinctrl-single is only controlling
the function mux, but it also controls the input/output buffer enable,
the pull-up and pull-down settings etc (pinctrl-single,function-mask
covers the entire pad setting instead of just the mux field).

Remove the pinctrl-single,gpio-range property, so that no settings are
applied during a gpio_request() call.

Fixes: 5e5c50964e2e ("arm64: dts: ti: k3-j722s: Add gpio-ranges properties")
Signed-off-by: Michael Walle <mwalle@kernel.org>
Link: https://lore.kernel.org/r/20250221091447.595199-2-mwalle@kernel.org
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-am62p: fix pinctrl settings

It appears that pinctrl-single is misused on this SoC to control both
the mux and the input and output and bias settings. This results in
non-working p

arm64: dts: ti: k3-am62p: fix pinctrl settings

It appears that pinctrl-single is misused on this SoC to control both
the mux and the input and output and bias settings. This results in
non-working pinctrl configurations for GPIOs within the device tree.

This is what happens:
(1) During startup the pinctrl settings are applied according to the
device tree. I.e. the pin is configured as output and with
pull-ups enabled.
(2) During startup a device driver requests a GPIO.
(3) pinctrl-single is applying the default GPIO setting according to
the pinctrl-single,gpio-range property.

This would work as expected if the pinctrl-single is only controlling
the function mux, but it also controls the input/output buffer enable,
the pull-up and pull-down settings etc (pinctrl-single,function-mask
covers the entire pad setting instead of just the mux field).

Remove the pinctrl-single,gpio-range property, so that no settings are
applied during a gpio_request() call.

Fixes: d72d73a44c3c ("arm64: dts: ti: k3-am62p: Add gpio-ranges properties")
Signed-off-by: Michael Walle <mwalle@kernel.org>
Link: https://lore.kernel.org/r/20250221091447.595199-1-mwalle@kernel.org
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: am64-phyboard-electra: Add DT overlay for X27 connector

Add a device tree overlay for SPI1 , UART3 and GPIO1 on
X27 connector.

By default, not all interfaces on the X27 connector ar

arm64: dts: ti: am64-phyboard-electra: Add DT overlay for X27 connector

Add a device tree overlay for SPI1 , UART3 and GPIO1 on
X27 connector.

By default, not all interfaces on the X27 connector are accessible
due to being disabled or set to alternative pin mux configurations.
This overlay activates and configures these interfaces to support
connections with external devices.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Link: https://lore.kernel.org/r/20250128100356.462934-1-d.schultz@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-j784s4-j742s2-main-common: Fix serdes_ln_ctrl reg-masks

Commit under Fixes added the 'idle-states' property for SERDES4 lane muxes
without defining the corresponding register offs

arm64: dts: ti: k3-j784s4-j742s2-main-common: Fix serdes_ln_ctrl reg-masks

Commit under Fixes added the 'idle-states' property for SERDES4 lane muxes
without defining the corresponding register offsets and masks for it in the
'mux-reg-masks' property within the 'serdes_ln_ctrl' node.

Fix this.

Fixes: 7287d423f138 ("arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux")
Cc: stable@vger.kernel.org
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20250228053850.506028-1-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-am62p: Enable AUDIO_REFCLKx

On AM62P-based SoCs the AUDIO_REFCLKx clocks can be used as an input to
external peripherals when configured through CTRL_MMR, so add the
clock nodes.

arm64: dts: ti: k3-am62p: Enable AUDIO_REFCLKx

On AM62P-based SoCs the AUDIO_REFCLKx clocks can be used as an input to
external peripherals when configured through CTRL_MMR, so add the
clock nodes.

Link: http://downloads.ti.com/tisci/esd/latest/5_soc_doc/am62px/clocks.html
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Link: https://lore.kernel.org/r/20250206153911.414702-1-francesco@dolcini.it
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-am62-phycore-som: Reserve RTOS IPC memory

Reserve a portion of memory for inter-processor communication between
all remote processors running RTOS or baremetal firmware.
Move ramo

arm64: dts: ti: k3-am62-phycore-som: Reserve RTOS IPC memory

Reserve a portion of memory for inter-processor communication between
all remote processors running RTOS or baremetal firmware.
Move ramoops to lower region so the IPC fits to the correct address.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20250131093531.1054924-2-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-am64-phycore-som: Reserve RTOS IPC memory

Reserve a portion of memory for inter-processor communication between
all remote processors running RTOS or baremetal firmware.

Signed-o

arm64: dts: ti: k3-am64-phycore-som: Reserve RTOS IPC memory

Reserve a portion of memory for inter-processor communication between
all remote processors running RTOS or baremetal firmware.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20250131093531.1054924-1-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-am62p5-sk: Add serial alias

Add alias for mcu_uart0.

Signed-off-by: Vibhore Vardhan <vibhore@ti.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Link: https://lor

arm64: dts: ti: k3-am62p5-sk: Add serial alias

Add alias for mcu_uart0.

Signed-off-by: Vibhore Vardhan <vibhore@ti.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Link: https://lore.kernel.org/r/20250203-topic-am62-serial-aliases-v6-14-v1-3-f26d4124a9f1@baylibre.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-am62a7-sk: Add serial alias

Add alias for mcu_uart0.

Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Link: https://lore.kernel.org/r/20250203-topic-am62-serial-aliase

arm64: dts: ti: k3-am62a7-sk: Add serial alias

Add alias for mcu_uart0.

Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Link: https://lore.kernel.org/r/20250203-topic-am62-serial-aliases-v6-14-v1-2-f26d4124a9f1@baylibre.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-am62x-sk-common: Add serial aliases

Add aliases for mcu_uart0 and wkup_uart0.

Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Link: https://lore.kernel.org/r/20250203

arm64: dts: ti: k3-am62x-sk-common: Add serial aliases

Add aliases for mcu_uart0 and wkup_uart0.

Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Link: https://lore.kernel.org/r/20250203-topic-am62-serial-aliases-v6-14-v1-1-f26d4124a9f1@baylibre.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-am62p5-sk: Support SoC wakeup using USB1 wakeup

After the SoC has entered the Deep Sleep mode, USB1 can be used to wakeup
the SoC based on USB events triggered by USB devices. Thi

arm64: dts: ti: k3-am62p5-sk: Support SoC wakeup using USB1 wakeup

After the SoC has entered the Deep Sleep mode, USB1 can be used to wakeup
the SoC based on USB events triggered by USB devices. This requires that
the pin corresponding to the Type-A connector remains pulled up even after
the SoC has entered the Deep Sleep mode. Hence, enable Deep Sleep pullup /
pulldown selection for the USB1_DRVBUS pin and set its Deep Sleep state to
PULL_UP.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20250130062550.1554651-1-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-am625-beagleplay: Reserve 128MiB of global CMA

In the same lines of commit 9e8560556f9c ("arm64: dts: ti:
k3-am62x-sk-common: Reserve 128MiB of global CMA"), reserve global CMA
po

arm64: dts: ti: k3-am625-beagleplay: Reserve 128MiB of global CMA

In the same lines of commit 9e8560556f9c ("arm64: dts: ti:
k3-am62x-sk-common: Reserve 128MiB of global CMA"), reserve global CMA
pool for:

LCD Display: 16MiB, HDMI (1080p): 16MiB, GPU: 16MiB, CSI2 1 1080p
sensor: 32MiB with a 32MiB set for other peripherals and a 16MiB
buffer.

Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20250131173508.1338842-1-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-j721e-sk: Add boot phase tag to SERDES3

The USB0 instance of USB on J721E SoC can be used for USB DFU boot.
Since the USB Type-C interface on the J721E-SK is connected to USB0 via

arm64: dts: ti: k3-j721e-sk: Add boot phase tag to SERDES3

The USB0 instance of USB on J721E SoC can be used for USB DFU boot.
Since the USB Type-C interface on the J721E-SK is connected to USB0 via
SERDES3, supporting USB DFU boot requires SERDES3 link associated with
USB0 to be functional at all stages of the USB DFU boot process. Thus,
add the "bootph-all" boot phase tag to "serdes3_usb_link" device-tree node.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20250209081738.1874749-3-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-j721e-common-proc-board: Add boot phase tag to SERDES3

The USB0 instance of USB on J721E SoC can be used for USB DFU boot.
Since the USB Type-C interface on the J721E-EVM is conne

arm64: dts: ti: k3-j721e-common-proc-board: Add boot phase tag to SERDES3

The USB0 instance of USB on J721E SoC can be used for USB DFU boot.
Since the USB Type-C interface on the J721E-EVM is connected to USB0 via
SERDES3, supporting USB DFU boot requires SERDES3 link associated with
USB0 to be functional at all stages of the USB DFU boot process. Thus,
add the "bootph-all" boot phase tag to "serdes3_usb_link" device-tree node.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20250209081738.1874749-2-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-am62p-j722s-common-wakeup: Configure ti-sysc for wkup_uart0

Similar to the TI K3-AM62x Soc commit ce27f7f9e328c8582a169f97f1466976561f1
("arm64: dts: ti: k3-am62-wakeup: Configure

arm64: dts: ti: k3-am62p-j722s-common-wakeup: Configure ti-sysc for wkup_uart0

Similar to the TI K3-AM62x Soc commit ce27f7f9e328c8582a169f97f1466976561f1
("arm64: dts: ti: k3-am62-wakeup: Configure ti-sysc for wkup_uart0")
The devices in the wkup domain are capable of waking up the system from
suspend. We can configure the wkup domain devices in a generic way using
the ti-sysc interconnect target module driver like we have done with the
earlier TI SoCs.

As ti-sysc manages the SYSCONFIG related registers independent of the
child hardware device, the wake-up configuration is also set even if
wkup_uart0 is reserved by sysfw.

The wkup_uart0 device has interconnect target module register mapping like
dra7 wkup uart. There is a 1 MB interconnect target range with one uart IP
block in the target module. The power domain and clock affects the whole
interconnect target module.

Note we change the functional clock name to follow the ti-sysc binding
and use "fck" instead of "fclk".

Also note that we need to disable the target module reset as noted by
Markus. Otherwise the sysfw using wkup_uart0 can get confused on some
devices leading to boot time issues such as mbox timeouts.

Signed-off-by: Vibhore Vardhan <vibhore@ti.com>
Signed-off-by: Kendall Willis <k-willis@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20250212215248.746838-1-k-willis@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-am62a7-sk: Add alias for RTC

Adds alias for SoC RTC so that it gets assigned rtc0. PMIC node is
assigned rtc1 so that PMIC RTC gets probed as rtc1. This makes it
consistent for te

arm64: dts: ti: k3-am62a7-sk: Add alias for RTC

Adds alias for SoC RTC so that it gets assigned rtc0. PMIC node is
assigned rtc1 so that PMIC RTC gets probed as rtc1. This makes it
consistent for testing rtcwake with other AM62 devices where rtc0
is SoC RTC.

Signed-off-by: Vibhore Vardhan <vibhore@ti.com>
[k-willis@ti.com: Reworded commit message]
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Kendall Willis <k-willis@ti.com>
Link: https://lore.kernel.org/r/20250214232212.1158505-1-k-willis@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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arm64: dts: ti: k3-j721s2-som-p0: Add flash partition details

When used as boot device, OSPI flash hosts different boot
binaries and rootfs etc.
So Add partition details for images hosted on OSPI f

arm64: dts: ti: k3-j721s2-som-p0: Add flash partition details

When used as boot device, OSPI flash hosts different boot
binaries and rootfs etc.
So Add partition details for images hosted on OSPI flash.

Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20250215070059.1593489-1-u-kumar1@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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