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fb28cef0 |
| 05-Nov-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: dts: uniphier: make compatible of syscon nodes SoC-specific
These hardware blocks are SoC-specific, so their compatible strings should be SoC-specific as well. This change has no impact on t
arm64: dts: uniphier: make compatible of syscon nodes SoC-specific
These hardware blocks are SoC-specific, so their compatible strings should be SoC-specific as well. This change has no impact on the actual behavior since it is controlled by the generic "simple-mfd", "syscon" compatible strings.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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bdb81836 |
| 20-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC
Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver.
Note: clock-latency-ns (300ns) was calculated
arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC
Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver.
Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
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1ef64af8 |
| 16-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: dts: uniphier: increase register region size of sysctrl node
The System Control node has 0x10000 byte of registers. The current reg size must be expanded to use the cpufreq driver because th
arm64: dts: uniphier: increase register region size of sysctrl node
The System Control node has 0x10000 byte of registers. The current reg size must be expanded to use the cpufreq driver because the registers controlling CPU frequency are located at offset 0x8000.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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2f81137f |
| 16-Oct-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: dts: uniphier: switch over to PSCI enable method
At the first system bring-up, I chose to use spin-table because ARM Trusted Firmware was not ready for this platform at that moment.
Actually
arm64: dts: uniphier: switch over to PSCI enable method
At the first system bring-up, I chose to use spin-table because ARM Trusted Firmware was not ready for this platform at that moment.
Actually, these SoCs are equipped with EL3 and able to provide PSCI. Now I finished porting the ATF BL31 for the UniPhier platform, so it is ready to migrate to PSCI enable method.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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cc9b9402 |
| 04-Nov-2016 |
Mark Brown <broonie@kernel.org> |
Merge branch 'topic/error' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator into regulator-fixed
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fe0f59c4 |
| 30-Oct-2016 |
Rafael J. Wysocki <rafael.j.wysocki@intel.com> |
Merge back earlier cpufreq material for v4.10.
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0fc4f78f |
| 25-Oct-2016 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
Merge remote-tracking branch 'airlied/drm-next' into topic/drm-misc
Backmerge latest drm-next to have a baseline for the s/fence/dma_fence/ patch from Chris.
Signed-off-by: Daniel Vetter <daniel.ve
Merge remote-tracking branch 'airlied/drm-next' into topic/drm-misc
Backmerge latest drm-next to have a baseline for the s/fence/dma_fence/ patch from Chris.
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
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f9bf1d97 |
| 25-Oct-2016 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queued
Backmerge because Chris Wilson needs the very latest&greates of Gustavo Padovan's sync_file work, specifically the refcount
Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queued
Backmerge because Chris Wilson needs the very latest&greates of Gustavo Padovan's sync_file work, specifically the refcounting changes from:
commit 30cd85dd6edc86ea8d8589efb813f1fad41ef233 Author: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Date: Wed Oct 19 15:48:32 2016 -0200
dma-buf/sync_file: hold reference to fence when creating sync_file
Also good to sync in general since git tends to get confused with the cherry-picking going on.
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
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aea98380 |
| 17-Oct-2016 |
Mauro Carvalho Chehab <mchehab@s-opensource.com> |
Merge tag 'v4.9-rc1' into patchwork
Linux 4.9-rc1
* tag 'v4.9-rc1': (13774 commits) Linux 4.9-rc1 score: traps: Add missing include file to fix build error fs/super.c: don't fool lockdep in f
Merge tag 'v4.9-rc1' into patchwork
Linux 4.9-rc1
* tag 'v4.9-rc1': (13774 commits) Linux 4.9-rc1 score: traps: Add missing include file to fix build error fs/super.c: don't fool lockdep in freeze_super() and thaw_super() paths fs/super.c: fix race between freeze_super() and thaw_super() overlayfs: Fix setting IOP_XATTR flag iov_iter: kernel-doc import_iovec() and rw_copy_check_uvector() CIFS: Retrieve uid and gid from special sid if enabled CIFS: Add new mount option to set owner uid and gid from special sids in acl qedr: Add events support and register IB device qedr: Add GSI support qedr: Add LL2 RoCE interface qedr: Add support for data path qedr: Add support for memory registeration verbs qedr: Add support for QP verbs qedr: Add support for PD,PKEY and CQ verbs qedr: Add support for user context verbs qedr: Add support for RoCE HW init qedr: Add RoCE driver framework pkeys: Remove easily triggered WARN MIPS: Wire up new pkey_{mprotect,alloc,free} syscalls ...
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4d69f155 |
| 16-Oct-2016 |
Ingo Molnar <mingo@kernel.org> |
Merge tag 'v4.9-rc1' into x86/fpu, to resolve conflict
Signed-off-by: Ingo Molnar <mingo@kernel.org>
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712cba5d |
| 07-Nov-2016 |
Max Filippov <jcmvbkbc@gmail.com> |
Merge tag 'v4.9-rc3' into xtensa-for-next
Linux 4.9-rc3
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8b2ada27 |
| 29-Oct-2016 |
Rafael J. Wysocki <rafael.j.wysocki@intel.com> |
Merge branches 'pm-cpufreq-fixes' and 'pm-sleep-fixes'
* pm-cpufreq-fixes: cpufreq: intel_pstate: Always set max P-state in performance mode cpufreq: intel_pstate: Set P-state upfront in perform
Merge branches 'pm-cpufreq-fixes' and 'pm-sleep-fixes'
* pm-cpufreq-fixes: cpufreq: intel_pstate: Always set max P-state in performance mode cpufreq: intel_pstate: Set P-state upfront in performance mode
* pm-sleep-fixes: PM / suspend: Fix missing KERN_CONT for suspend message
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1d33369d |
| 16-Oct-2016 |
Ingo Molnar <mingo@kernel.org> |
Merge tag 'v4.9-rc1' into x86/urgent, to pick up updates
Signed-off-by: Ingo Molnar <mingo@kernel.org>
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a439f8f2 |
| 08-Oct-2016 |
Linus Torvalds <torvalds@linux-foundation.org> |
Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Arnd Bergmann: "The 64-bit DT changes are surprisingly small this time, we only
Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Arnd Bergmann: "The 64-bit DT changes are surprisingly small this time, we only add two SoC platforms: the ZTE ZX296718 Set-top-box SoC and the SocioNext UniPhier LD11 TV SoC, each with their reference boards.
There are three new machines added for existing SoC platforms:
- The Marvell Armada 8040 development board is an impressive quad-core Cortex-A72 machine with three 10gbit ethernet interfaces
- Qualcomms DragonBoard 820c single-board computer is their current high-end phone platform in the 96boards form factor
- Rockchip: Tronsmart Orion r86 set-top-box is a popular mid-range Android box based on the 8-core rk3368 SoC"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (91 commits) arm64: dts: berlin4ct: Add L2 cache topology arm64: dts: berlin4ct: enable all wdt nodes unconditionally arm64: dts: berlin4ct: switch to Cortex-A53 specific pmu nodes arm64: dts: Add ZTE ZX296718 SoC dts and Makefile arm64: dts: apm: Add DT node for APM X-Gene 2 CPU clocks arm64: dts: apm: Add X-Gene SoC hwmon to device tree arm64: dts: apm: Fix interrupt polarity for X-Gene PCIe legacy interrupts arm64: dts: apm: Add APM X-Gene v2 SoC PMU DTS entries arm64: dts: apm: Add APM X-Gene SoC PMU DTS entries arm64: dts: marvell: enable MSI for PCIe on Armada 7K/8K arm64: dts: ls2080a: Add 'dma-coherent' for ls2080a PCI nodes arm64: dts: rockchip: add Type-C phy for RK3399 arm64: dts: rockchip: enable the gmac for rk3399 evb board arm64: dts: rockchip: add the gmac needed node for rk3399 arm64: dts: rockchip: support the pmu node for rk3399 arm64: dts: rockchip: change all interrupts cells to 4 on rk3399 SoCs arm64: dts: rockchip: add the tcpc for rk3399 power domain arm64: dts: rockchip: add efuse0 device node for rk3399 arm64: dts: rockchip: configure PCIe support for rk3399-evb arm64: dts: rockchip: add the PCIe controller support for RK3399 ...
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9b2a8b8b |
| 14-Sep-2016 |
Arnd Bergmann <arnd@arndb.de> |
Merge tag 'uniphier-dt64-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt64
Merge "UniPhier ARM64 SoC DT updates for v4.9" from Masahiro Yamada:
* Match
Merge tag 'uniphier-dt64-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt64
Merge "UniPhier ARM64 SoC DT updates for v4.9" from Masahiro Yamada:
* Match DT names other projects and documents * Use clock/reset drivers * Add new SoC/board support * Misc
* tag 'uniphier-dt64-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier: arm64: dts: uniphier: add LD11 SoC/Board support arm64: dts: uniphier: add specific compatible to SoC-Glue node arm64: dts: uniphier: use clock/reset controllers arm64: dts: uniphier: add pinctrl property to System Bus node arm64: dts: uniphier: match DT names to other projects and documents
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270e0c3e |
| 30-Aug-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
arm64: dts: uniphier: add LD11 SoC/Board support
This is a low-cost 64bit SoC from Socionext.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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