| 7dfe67ab | 31-Oct-2025 |
Jun Guo <jun.guo@cixtech.com> |
arm64: dts: cix: add a compatible string for the cix sky1 SoC
The SPI IP design for the cix sky1 SoC uses a FIFO with a data width of 32 bits, instead of the default 8 bits. Therefore, a compatible
arm64: dts: cix: add a compatible string for the cix sky1 SoC
The SPI IP design for the cix sky1 SoC uses a FIFO with a data width of 32 bits, instead of the default 8 bits. Therefore, a compatible string is added to specify the FIFO data width configuration for the cix sky1 SoC.
Signed-off-by: Jun Guo <jun.guo@cixtech.com> Link: https://lore.kernel.org/r/20251031073003.3289573-4-jun.guo@cixtech.com Signed-off-by: Peter Chen <peter.chen@cixtech.com>
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| b2bc5a82 | 08-Nov-2025 |
Hans Zhang <hans.zhang@cixtech.com> |
arm64: dts: cix: Enable PCIe on the Orion O6 board
Add PCIe RC support on Orion O6 board.
The Orion O6 board includes multiple PCIe root complexes. The current device tree configuration enables det
arm64: dts: cix: Enable PCIe on the Orion O6 board
Add PCIe RC support on Orion O6 board.
The Orion O6 board includes multiple PCIe root complexes. The current device tree configuration enables detection and basic operation of PCIe endpoints on this platform.
GPIO and pinctrl subsystems for this platform are not yet ready for upstream inclusion. Consequently, attributes such as reset-gpios and pinctrl configurations are temporarily omitted from the PCIe node definitions.
Endpoint detection and functionality are confirmed to be operational with this basic configuration. The missing GPIO and pinctrl support will be added incrementally in future patches as the dependent subsystems become available upstream.
Acked-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Hans Zhang <hans.zhang@cixtech.com> Link: https://lore.kernel.org/r/20251108140305.1120117-11-hans.zhang@cixtech.com Signed-off-by: Peter Chen <peter.chen@cixtech.com>
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| 0b014cd8 | 08-Nov-2025 |
Hans Zhang <hans.zhang@cixtech.com> |
arm64: dts: cix: Add PCIe Root Complex on sky1
Add pcie_x*_rc node to support Sky1 PCIe driver based on the Cadence PCIe core.
Supports Gen1/Gen2/Gen3/Gen4, 1/2/4/8 lane, MSI/MSI-x interrupts using
arm64: dts: cix: Add PCIe Root Complex on sky1
Add pcie_x*_rc node to support Sky1 PCIe driver based on the Cadence PCIe core.
Supports Gen1/Gen2/Gen3/Gen4, 1/2/4/8 lane, MSI/MSI-x interrupts using the ARM GICv3.
Acked-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Hans Zhang <hans.zhang@cixtech.com> Link: https://lore.kernel.org/r/20251108140305.1120117-10-hans.zhang@cixtech.com Signed-off-by: Peter Chen <peter.chen@cixtech.com>
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