|
Revision tags: v6.18, v6.18-rc7, v6.18-rc6, v6.18-rc5, v6.18-rc4 |
|
| #
cb9f145f |
| 01-Nov-2025 |
Rob Clark <robin.clark@oss.qualcomm.com> |
Merge remote-tracking branch 'drm/drm-next' into msm-next-robclark
Back-merge drm-next to get caught up.
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
|
|
Revision tags: v6.18-rc3, v6.18-rc2, v6.18-rc1, v6.17, v6.17-rc7 |
|
| #
f088104d |
| 16-Sep-2025 |
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> |
Merge drm/drm-next into drm-intel-gt-next
Backmerge in order to get the commit:
048832a3f400 ("drm/i915: Refactor shmem_pwrite() to use kiocb and write_iter")
To drm-intel-gt-next as there are f
Merge drm/drm-next into drm-intel-gt-next
Backmerge in order to get the commit:
048832a3f400 ("drm/i915: Refactor shmem_pwrite() to use kiocb and write_iter")
To drm-intel-gt-next as there are followup fixes to be applied.
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
show more ...
|
|
Revision tags: v6.17-rc6, v6.17-rc5, v6.17-rc4, v6.17-rc3, v6.17-rc2, v6.17-rc1 |
|
| #
a53d0cf7 |
| 05-Aug-2025 |
Ingo Molnar <mingo@kernel.org> |
Merge commit 'linus' into core/bugs, to resolve conflicts
Resolve conflicts with this commit that was developed in parallel during the merge window:
8c8efa93db68 ("x86/bug: Add ARCH_WARN_ASM macro
Merge commit 'linus' into core/bugs, to resolve conflicts
Resolve conflicts with this commit that was developed in parallel during the merge window:
8c8efa93db68 ("x86/bug: Add ARCH_WARN_ASM macro for BUG/WARN asm code sharing with Rust")
Conflicts: arch/riscv/include/asm/bug.h arch/x86/include/asm/bug.h
Signed-off-by: Ingo Molnar <mingo@kernel.org>
show more ...
|
| #
8b87f67b |
| 08-Oct-2025 |
Dmitry Torokhov <dmitry.torokhov@gmail.com> |
Merge branch 'next' into for-linus
Prepare input updates for 6.18 merge window.
|
| #
4b051897 |
| 21-Aug-2025 |
Dmitry Torokhov <dmitry.torokhov@gmail.com> |
Merge tag 'v6.17-rc2' into HEAD
Sync up with mainline to bring in changes to include/linux/sprintf.h
|
| #
b4d90dbc |
| 15-Sep-2025 |
Thomas Zimmermann <tzimmermann@suse.de> |
Merge drm/drm-next into drm-misc-next-fixes
Backmerging to drm-misc-next-fixes to get features and fixes from v6.17-rc6.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
|
| #
702fdf35 |
| 10-Sep-2025 |
Rodrigo Vivi <rodrigo.vivi@intel.com> |
Merge drm/drm-next into drm-intel-next
Catching up with some display dependencies.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
|
| #
ca994e89 |
| 12-Aug-2025 |
Lucas De Marchi <lucas.demarchi@intel.com> |
Merge drm/drm-next into drm-xe-next
Bring v6.17-rc1 to propagate commits from other subsystems, particularly PCI, which has some new functions needed for SR-IOV integration.
Signed-off-by: Lucas De
Merge drm/drm-next into drm-xe-next
Bring v6.17-rc1 to propagate commits from other subsystems, particularly PCI, which has some new functions needed for SR-IOV integration.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
show more ...
|
| #
08c51f5b |
| 11-Aug-2025 |
Thomas Zimmermann <tzimmermann@suse.de> |
Merge drm/drm-next into drm-misc-n
Updating drm-misc-next to the state of v6.17-rc1. Begins a new release cycle.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
|
| #
8d2b0853 |
| 11-Aug-2025 |
Thomas Zimmermann <tzimmermann@suse.de> |
Merge drm/drm-fixes into drm-misc-fixes
Updating drm-misc-fixes to the state of v6.17-rc1. Begins a new release cycle.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
|
| #
4df9c0a2 |
| 29-Jul-2025 |
Linus Torvalds <torvalds@linux-foundation.org> |
Merge tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull new SoC support from Arnd Bergmann: "These five newly supported chips come with both devicetree descripti
Merge tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull new SoC support from Arnd Bergmann: "These five newly supported chips come with both devicetree descriptions and the changes to wire them up to the build system for easier bisection.
The chips in question are:
- Marvell PXA1908 was the first 64-bit mobile phone chip from Marvell in the product line that started with the Digital StrongARM SA1100 based PDAs and continued with the Intel PXA2xx that dominated early smartphones. This one only made it only into a few products before the entire product line was cut in 2015.
- The QiLai SoC is made by RISC-V core designer Andes Technologies and is in the 'Voyager' reference board in MicroATX form factor. It uses four in-order AX45MP cores, which is the midrange product from Andes.
- CIX P1 is one of the few Arm chips designed for small workstations, and this one uses 12 Cortex-A720/A520 cores, making it also one of the only ARMv9.2 machines that one can but at the moment.
- Axiado AX3000 is an embedded chip with relative small Cortex-A53 CPU cores described as a "Trusted Control/Compute Unit" that can be used as a BMC in servers. In addition to the usual I/O, this one comes with 10GBit ethernet and and a 4TOPS NPU.
- Sophgo SG2000 is an embedded chip that comes with both RISC-V and Arm cores that can run Linux. This was already supported for RISC-V but now it also works on Arm
One more chip, the Black Sesame C1200 did not make it in tirm for the merge window"
* tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits) arm64: defconfig: Enable rudimentary Sophgo SG2000 support arm64: Add SOPHGO SOC family Kconfig support arm64: dts: sophgo: Add Duo Module 01 Evaluation Board arm64: dts: sophgo: Add Duo Module 01 arm64: dts: sophgo: Add initial SG2000 SoC device tree MAINTAINERS: Add entry for Axiado arm64: defconfig: enable the Axiado family arm64: dts: axiado: Add initial support for AX3000 SoC and eval board arm64: add Axiado SoC family dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller dt-bindings: serial: cdns: add Axiado AX3000 UART controller dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant dt-bindings: gpio: cdns: convert to YAML dt-bindings: arm: axiado: add AX3000 EVK compatible strings dt-bindings: vendor-prefixes: Add Axiado Corporation MAINTAINERS: Add CIX SoC maintainer entry arm64: dts: cix: Add sky1 base dts initial support dt-bindings: clock: cix: Add CIX sky1 scmi clock id arm64: defconfig: Enable CIX SoC mailbox: add CIX mailbox driver ...
show more ...
|
|
Revision tags: v6.16 |
|
| #
dceb3667 |
| 22-Jul-2025 |
Arnd Bergmann <arnd@arndb.de> |
Merge branch 'newsoc/axiado' into soc/newsoc
Support for the AX3000 SoC, from Harshit Shah <hshah@axiado.com>:
The AX3000 is a multi-core system-on-chip featuring four ARM Cortex-A53 cores, secure
Merge branch 'newsoc/axiado' into soc/newsoc
Support for the AX3000 SoC, from Harshit Shah <hshah@axiado.com>:
The AX3000 is a multi-core system-on-chip featuring four ARM Cortex-A53 cores, secure vault, hardware firewall, and AI acceleration engines. This initial support enables basic bring-up of the SoC and evaluation platform with CPU, timer, UART, and I3C functionality.
The series begins by adding the "axiado" vendor prefix and compatible strings for the SoC and board. It then introduces the device tree files and minimal ARCH_AXIADO platform support in arm64.
* newsoc/axiado: MAINTAINERS: Add entry for Axiado arm64: defconfig: enable the Axiado family arm64: dts: axiado: Add initial support for AX3000 SoC and eval board arm64: add Axiado SoC family dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller dt-bindings: serial: cdns: add Axiado AX3000 UART controller dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant dt-bindings: gpio: cdns: convert to YAML dt-bindings: arm: axiado: add AX3000 EVK compatible strings dt-bindings: vendor-prefixes: Add Axiado Corporation
show more ...
|
| #
1f705577 |
| 22-Jul-2025 |
Harshit Shah <hshah@axiado.com> |
arm64: dts: axiado: Add initial support for AX3000 SoC and eval board
Add initial device tree support for the AX3000 SoC and its evaluation platform. The AX3000 is a multi-core SoC featuring 4 Corte
arm64: dts: axiado: Add initial support for AX3000 SoC and eval board
Add initial device tree support for the AX3000 SoC and its evaluation platform. The AX3000 is a multi-core SoC featuring 4 Cortex-A53 cores, Secure Vault, AI Engine and Firewall.
It adds support for Cortex-A53 CPUs, timer, UARTs, and I3C controllers on the AX3000 evaluation board.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Harshit Shah <hshah@axiado.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
show more ...
|