Merge branch 'next' into for-linus

Prepare input updates for 5.3 merge window.

Merge tag 'v5.1' into next

Sync up with mainline to bring in the latest APIs.

Merge tag 'drm-intel-next-2019-04-04' into gvt-next

Merge back drm-intel-next for engine name definition refinement
and 54939ea0bd85 ("drm/i915: Switch to use HWS indices rather than addresses")
tha

Merge tag 'drm-intel-next-2019-04-04' into gvt-next

Merge back drm-intel-next for engine name definition refinement
and 54939ea0bd85 ("drm/i915: Switch to use HWS indices rather than addresses")
that would need gvt fixes to depend on.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

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Merge tag 'v5.0-rc5' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into fbdev-for-next

Linux 5.0-rc5

Sync with upstream (which now contains fbdev-v5.0-rc3 changes) to
prepare a

Merge tag 'v5.0-rc5' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into fbdev-for-next

Linux 5.0-rc5

Sync with upstream (which now contains fbdev-v5.0-rc3 changes) to
prepare a base for fbdev-v5.1 changes.

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Merge drm/drm-next into drm-misc-next

drm-next has been forwarded to 5.0-rc1, and we need it to apply the damage
helper for dirtyfb series from Noralf Trønnes.

Signed-off-by: Maxime Ripard <maxime.

Merge drm/drm-next into drm-misc-next

drm-next has been forwarded to 5.0-rc1, and we need it to apply the damage
helper for dirtyfb series from Noralf Trønnes.

Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

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Merge tag 'v5.0-rc1' into next-general

Linux 5.0-rc1

Sync to pick up LSM stacking work (which is based on -rc1).

Merge drm/drm-next into drm-intel-next-queued

Generally catch up with 5.0-rc1, and specifically get the changes:

96d4f267e40f ("Remove 'type' argument from access_ok() function")
0b2c8f8b6b0c ("i91

Merge drm/drm-next into drm-intel-next-queued

Generally catch up with 5.0-rc1, and specifically get the changes:

96d4f267e40f ("Remove 'type' argument from access_ok() function")
0b2c8f8b6b0c ("i915: fix missing user_access_end() in page fault exception case")
594cc251fdd0 ("make 'user_access_begin()' do 'access_ok()'")

Signed-off-by: Jani Nikula <jani.nikula@intel.com>

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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"This round is dominated by NXP's i.MX clk drivers. We gained support
for

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"This round is dominated by NXP's i.MX clk drivers. We gained support
for two or three i.MX SoCs in here and that mostly means a lot of
driver code and data.

Beyond that platform, there are some new Mediatek, Amlogic, and
Qualcomm clk drivers added in here, and then we get to the long tail
of driver updates and non-critical fixes all around, including code
for vendors such as Renesas, Rockchip, Nvidia, and Allwinner. Overall,
the driver updates look normal.

Apart from the usual driver updates we have an update to make
registering OF based clk providers a little simpler when they're
devices created as a child of a device backed by a node in DT. Drivers
don't have to jump through hoops to unregister the provider upon
driver removal anymore because the API does the right thing and uses
the parent device DT node.

Summary:

Core:
- Make devm_of_clk_add_hw_provider() use parent dt node if necessary
- Various SPDX taggings
- Mark clk_ops const when possible

New Drivers:
- NXP i.MX7ULP SoC clock support
- NXP i.MX8QXP SoC clock support
- NXP i.MX8MQ SoC clock support
- NXP QorIQ T1023 SoC support
- Qualcomm SDM845 audio subsystem clks
- Qualcomm SDM845 GPU clck controllers
- Qualcomm QCS404 RPM clk support
- Mediatek MT7629 SoC clk controllers
- Allwinner F1c100s SoC clocks
- Allwinner H6 display engine clocks
- Amlogic GX video clocks
- Support for Amlogic meson8b CPU frequency scaling
- Amlogic Meson8b CPU post-divider clocks

Updates:
- Proper suspend/resume on VersaClock5
- Shrink code some with DEFINE_SHOW_ATTRIBUTE()
- Register fixes for Rockchip rk3188 and rk3328
- One new critical clock for Rockchip rk3188 and a fixed clock id
(double used number)
- New clock id for Rockchip rk3328
- Amlogic Meson8/Meson8b video clock support
- Amlogic got a clk-input helper and used it for the axg-audio clock
driver
- Sigma Delta modulation for the Allwinner A33 audio clocks
- Support for CPEX (timer) clocks on various Renesas R-Car Gen3 and
RZ/G2 SoCs
- Support for SDHI HS400 clocks on early revisions of Renesas R-Car
H3 and M3-W
- Support for SDHI and USB clocks on Renesas RZ/A2
- Support for RPC (SPI Multi I/O Bus Controller) clocks on Renesas
R-Car V3M
- Qualcomm MSM8998 GCC driver improvements (resets, drop unused clks,
etc)"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (172 commits)
clk: imx: imx7ulp: add arm hsrun mode clocks support
dt-bindings: clock: imx7ulp: add HSRUN mode related clocks
clk: Use of_node_name_eq for node name comparisons
clk: vc5: Add suspend/resume support
clk: qcom: Drop unused 8998 clock
clk: qcom: Leave mmss noc on for 8998
clk: tegra: Return the exact clock rate from clk_round_rate
clk: tegra30: Use Tegra CPU powergate helper function
soc/tegra: pmc: Drop SMP dependency from CPU APIs
clk: tegra: Fix maximum audio sync clock for Tegra124/210
clk: tegra: get rid of duplicate defines
clk: imx: add imx8qxp lpcg driver
clk: imx: add lpcg clock support
clk: imx: add imx8qxp clk driver
clk: imx: Make the i.MX8MQ CCM clock driver CLK_IMX8MQ dependant
clk: imx: add scu clock common part
clk: imx: add configuration option for mmio clks
dt-bindings: clock: add imx8qxp lpcg clock binding
dt-bindings: clock: imx8qxp: add SCU clock IDs
clk: qcom: Add missing msm8998 resets
...

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Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and 'clk-rockchip' into clk-next

* clk-renesas:
clk: renesas: rcar-gen3: Add HS400 quirk for SD clock
clk: renesas: rcar-g

Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and 'clk-rockchip' into clk-next

* clk-renesas:
clk: renesas: rcar-gen3: Add HS400 quirk for SD clock
clk: renesas: rcar-gen3: Add documentation for SD clocks
clk: renesas: rcar-gen3: Set state when registering SD clocks
clk: renesas: r8a77995: Simplify PLL3 multiplier/divider
clk: renesas: r8a77995: Add missing CPEX clock
clk: renesas: r8a77995: Remove non-existent SSP clocks
clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks
clk: renesas: r8a77995: Correct parent clock of DU
clk: renesas: r8a77990: Correct parent clock of DU
clk: renesas: r8a77970: Add CPEX clock
clk: renesas: r8a77965: Add CPEX clock
clk: renesas: r8a7796: Add CPEX clock
clk: renesas: r8a7795: Add CPEX clock
clk: renesas: r8a774a1: Add CPEX clock
dt-bindings: clock: r8a7796: Remove CSIREF clock
dt-bindings: clock: r8a7795: Remove CSIREF clock
clk: renesas: Mark rza2_cpg_clk_register static
clk: renesas: r7s9210: Add USB clocks
clk: renesas: r8a77970: Add RPC clocks
clk: renesas: r7s9210: Add SDHI clocks

* clk-allwinner:
clk: sunxi-ng: a64: Allow parent change for VE clock
clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks
clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLL
clk: sunxi-ng: h3: Allow parent change for ve clock
clk: sunxi-ng: add support for suniv F1C100s SoC
dt-bindings: clock: Add Allwinner suniv F1C100s CCU
clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent
clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output
clk: sunxi-ng: sun50i: a64: Use sigma-delta modulation for audio PLL
clk: sunxi-ng: a64: Fix gate bit of DSI DPHY
clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I
clk: sunxi-ng: Add support for H6 DE3 clocks
dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description
clk: sunxi-ng: h6: Set video PLLs limits
clk: sunxi-ng: Use u64 for calculation of NM rate
clk: sunxi-ng: Adjust MP clock parent rate when allowed
clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width
clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clock

* clk-tegra:
clk: tegra: Return the exact clock rate from clk_round_rate
clk: tegra30: Use Tegra CPU powergate helper function
soc/tegra: pmc: Drop SMP dependency from CPU APIs
clk: tegra: Fix maximum audio sync clock for Tegra124/210
clk: tegra: get rid of duplicate defines
clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC
clk: tegra20: Turn EMC clock gate into divider

* clk-meson: (25 commits)
clk: meson: axg-audio: use the clk input helper function
clk: meson: add clk-input helper function
clk: meson: Mark some things static
clk: meson: meson8b: add the read-only video clock trees
clk: meson: meson8b: add the fractional divider for vid_pll_dco
clk: meson: meson8b: fix the offset of vid_pll_dco's N value
clk: meson: Fix GXL HDMI PLL fractional bits width
clk: meson: meson8b: add the CPU clock post divider clocks
clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3
clk: meson: clk-regmap: add read-only gate ops
clk: meson: meson8b: allow changing the CPU clock tree
clk: meson: meson8b: run from the XTAL when changing the CPU frequency
clk: meson: meson8b: add support for more M/N values in sys_pll
clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL
clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel
clk: meson: clk-pll: check if the clock is already enabled
clk: meson: meson8b: fix the width of the cpu_scale_div clock
clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table
clk: meson: meson8b: use the HHI syscon if available
dt-bindings: clock: meson8b: use the registers from the HHI syscon
...

* clk-rockchip:
clk: rockchip: add clock-id to gate of ACODEC for rk3328
clk: rockchip: add clock ID of ACODEC for rk3328
clk: rockchip: fix ID of 8ch clock of I2S1 for rk3328
clk: rockchip: fix I2S1 clock gate register for rk3328
clk: rockchip: make rk3188 hclk_vio_bus critical
clk: rockchip: fix rk3188 sclk_mac_lbtest parameter ordering
clk: rockchip: fix rk3188 sclk_smc gate data
clk: rockchip: fix typo in rk3188 spdif_frac parent

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Merge tag 'sunxi-clk-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clock changes from Maxime Ripard:

- Sigma Delta modulation for the A

Merge tag 'sunxi-clk-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clock changes from Maxime Ripard:

- Sigma Delta modulation for the A33 audio clocks
- Support for the F1c100s SoC
- Rework of the oscillator tree
- H6 display engine clocks

* tag 'sunxi-clk-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks
clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLL
clk: sunxi-ng: h3: Allow parent change for ve clock
clk: sunxi-ng: add support for suniv F1C100s SoC
dt-bindings: clock: Add Allwinner suniv F1C100s CCU
clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent
clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output
clk: sunxi-ng: sun50i: a64: Use sigma-delta modulation for audio PLL
clk: sunxi-ng: a64: Fix gate bit of DSI DPHY
clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I
clk: sunxi-ng: Add support for H6 DE3 clocks
dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description
clk: sunxi-ng: h6: Set video PLLs limits
clk: sunxi-ng: Use u64 for calculation of NM rate
clk: sunxi-ng: Adjust MP clock parent rate when allowed
clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width
clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clock

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dt-bindings: clock: Add Allwinner suniv F1C100s CCU

Add compatiple string for Allwinner suniv F1C100s CCU.
Add clock and reset definitions.

Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
Acked

dt-bindings: clock: Add Allwinner suniv F1C100s CCU

Add compatiple string for Allwinner suniv F1C100s CCU.
Add clock and reset definitions.

Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

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