| 863515d1 | 14-May-2026 |
Kartik Rajput <kkartik@nvidia.com> |
soc/tegra: fuse: Use device-specific instance in suspend/resume
Avoid using the default fuse instance in suspend/resume callbacks, as it always runs the suspend/resume callbacks for the default inst
soc/tegra: fuse: Use device-specific instance in suspend/resume
Avoid using the default fuse instance in suspend/resume callbacks, as it always runs the suspend/resume callbacks for the default instance rather than the device’s own.
Get the correct fuse instance by using `dev_get_drvdata()`.
Signed-off-by: Kartik Rajput <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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| 265d5d40 | 04-Jun-2026 |
Breno Leitao <leitao@debian.org> |
soc/tegra: fuse: Fix spurious straps warning on SMCCC platforms
My Grace host started to show this warning: WARNING: drivers/soc/tegra/fuse/tegra-apbmisc.c:120 at tegra_read_straps tegra30_fuse
soc/tegra: fuse: Fix spurious straps warning on SMCCC platforms
My Grace host started to show this warning: WARNING: drivers/soc/tegra/fuse/tegra-apbmisc.c:120 at tegra_read_straps tegra30_fuse_add_randomness tegra30_fuse_init tegra_fuse_probe
tegra_read_straps() warns when the static "chipid" cache is still zero, using it as a proxy for "APBMISC has been initialised". However chipid is only ever populated lazily by tegra_read_chipid() when it reads the APBMISC register.
Guard on apbmisc_base instead, which is set unconditionally in tegra_init_apbmisc_resources() for all platforms and is already the sentinel used by tegra_read_chipid().
Fixes: 8b8ee2e56f95 ("soc/tegra: Use ARM SMCCC to get chip ID, revision, and platform info") Signed-off-by: Breno Leitao <leitao@debian.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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| 8b8ee2e5 | 14-May-2026 |
Kartik Rajput <kkartik@nvidia.com> |
soc/tegra: Use ARM SMCCC to get chip ID, revision, and platform info
Tegra410 and Tegra241 deprecate the HIDREV register. The recommended method is to use ARM SMCCC to retrieve the chip ID, major an
soc/tegra: Use ARM SMCCC to get chip ID, revision, and platform info
Tegra410 and Tegra241 deprecate the HIDREV register. The recommended method is to use ARM SMCCC to retrieve the chip ID, major and minor revisions, and platform information.
Prefer ARM SMCCC when the platform supports it; fall back to HIDREV otherwise. Behavior on older Tegra SoCs that do not support ARM SMCCC remains unchanged.
Signed-off-by: Kartik Rajput <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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| 688dfe40 | 22-Oct-2025 |
Aaron Kling <webgeek1234@gmail.com> |
soc/tegra: fuse: speedo-tegra210: Add SoC speedo 2
The Jetson Nano series of modules only have 2 EMC table entries, different from other SoC SKUs. As the EMC driver uses the SoC speedo ID to populat
soc/tegra: fuse: speedo-tegra210: Add SoC speedo 2
The Jetson Nano series of modules only have 2 EMC table entries, different from other SoC SKUs. As the EMC driver uses the SoC speedo ID to populate the EMC OPP tables, add a new speedo ID to uniquely identify this.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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| ce27c9c2 | 23-Sep-2025 |
Aaron Kling <webgeek1234@gmail.com> |
soc/tegra: fuse: speedo-tegra210: Update speedo IDs
Existing code only sets CPU and GPU speedo IDs 0 and 1. The CPU DVFS code supports 11 IDs and nouveau supports 5. This aligns with what the downst
soc/tegra: fuse: speedo-tegra210: Update speedo IDs
Existing code only sets CPU and GPU speedo IDs 0 and 1. The CPU DVFS code supports 11 IDs and nouveau supports 5. This aligns with what the downstream vendor kernel supports. Align SKUs with the downstream list.
The Tegra210 CVB tables were added in the first referenced fixes commit. Since then, all Tegra210 SoCs have tried to scale to 1.9 GHz, when the supported devkits are only supposed to scale to 1.5 or 1.7 GHZ. Overclocking should not be the default state.
Fixes: 2b2dbc2f94e5 ("clk: tegra: dfll: add CVB tables for Tegra210") Fixes: 579db6e5d9b8 ("arm64: tegra: Enable DFLL support on Jetson Nano") Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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| d820100a | 03-Jan-2024 |
Arnd Bergmann <arnd@arndb.de> |
soc/tegra: Fix build failure on Tegra241
If all the other SoCs are disabled, the driver fails to build:
drivers/soc/tegra/fuse/fuse-tegra30.c:684:17: error: 'tegra30_fuse_read' undeclared here (not
soc/tegra: Fix build failure on Tegra241
If all the other SoCs are disabled, the driver fails to build:
drivers/soc/tegra/fuse/fuse-tegra30.c:684:17: error: 'tegra30_fuse_read' undeclared here (not in a function); did you mean 'tegra_fuse_readl'? 684 | .read = tegra30_fuse_read, | ^~~~~~~~~~~~~~~~~ | tegra_fuse_readl drivers/soc/tegra/fuse/fuse-tegra30.c:694:17: error: 'tegra30_fuse_init' undeclared here (not in a function); did you mean 'tegra_fuse_info'? 694 | .init = tegra30_fuse_init, | ^~~~~~~~~~~~~~~~~
Fix the list of SoCs using this function to include the newly added one.
Fixes: dee509eb9cd5 ("soc/tegra: fuse: Add support for Tegra241") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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| 81b3f0ef | 29-Jan-2024 |
Jon Hunter <jonathanh@nvidia.com> |
soc/tegra: fuse: Fix crash in tegra_fuse_readl()
Commit c5b2d43e67bb ("soc/tegra: fuse: Add ACPI support for Tegra194 and Tegra234") updated the Tegra fuse driver to add ACPI support and added a tes
soc/tegra: fuse: Fix crash in tegra_fuse_readl()
Commit c5b2d43e67bb ("soc/tegra: fuse: Add ACPI support for Tegra194 and Tegra234") updated the Tegra fuse driver to add ACPI support and added a test to the tegra_fuse_readl() function to check if the device is booting with device-tree. This test passes 'fuse->dev' variable to dev_fwnode() but does not check first is 'fuse->dev' is valid. This is causing a crash to occur in Tegra XUSB PHY driver that calls the tegra_fuse_readl() function before 'fuse->dev' variable has been initialised ...
Unable to handle kernel NULL pointer dereference at virtual address 0000000000000290 Mem abort info: ESR = 0x0000000096000004 EC = 0x25: DABT (current EL), IL = 32 bits SET = 0, FnV = 0 EA = 0, S1PTW = 0 FSC = 0x04: level 0 translation fault Data abort info: ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000 CM = 0, WnR = 0, TnD = 0, TagAccess = 0 GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0 [0000000000000290] user address but active_mm is swapper Internal error: Oops: 0000000096000004 [#1] PREEMPT SMP Modules linked in: CPU: 7 PID: 70 Comm: kworker/u16:4 Not tainted 6.8.0-rc1-next-20240129-02825-g596764183be8 #1 Hardware name: NVIDIA Jetson AGX Xavier Developer Kit (DT) Workqueue: events_unbound deferred_probe_work_func pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : __dev_fwnode+0x0/0x18 lr : tegra_fuse_readl+0x24/0x98 sp : ffff80008393ba10 x29: ffff80008393ba10 x28: 0000000000000000 x27: ffff800081233c10 x26: 00000000000001c8 x25: ffff000080b7bc10 x24: ffff000082df3b00 x23: fffffffffffffff4 x22: 0000000000000004 x21: ffff80008393ba84 x20: 00000000000000f0 x19: ffff800082f1e000 x18: ffff800081d72000 x17: 0000000000000001 x16: 0000000000000001 x15: ffff800082fcdfff x14: 0000000000000000 x13: 0000000003541000 x12: 0000000000000020 x11: 0140000000000000 x10: ffff800080000000 x9 : 0000000000000000 x8 : ffff000082df3b40 x7 : 0000000000000000 x6 : 000000000000003f x5 : 00000000ffffffff x4 : 0000000000000dc0 x3 : 00000000000000c0 x2 : 0000000000000001 x1 : ffff80008393ba84 x0 : 0000000000000000 Call trace: __dev_fwnode+0x0/0x18 tegra186_xusb_padctl_probe+0xb0/0x1a8 tegra_xusb_padctl_probe+0x7c/0xebc platform_probe+0x90/0xd8 really_probe+0x13c/0x29c __driver_probe_device+0x7c/0x124 driver_probe_device+0x38/0x11c __device_attach_driver+0x90/0xdc bus_for_each_drv+0x78/0xdc __device_attach+0xfc/0x188 device_initial_probe+0x10/0x18 bus_probe_device+0xa4/0xa8 deferred_probe_work_func+0x80/0xb4 process_scheduled_works+0x178/0x3e0 worker_thread+0x164/0x2e8 kthread+0xfc/0x11c ret_from_fork+0x10/0x20 Code: a8c27bfd d65f03c0 128002a0 d65f03c0 (f9414801) ---[ end trace 0000000000000000 ]---
Fix this by verifying that 'fuse->dev' is valid before passing to dev_fwnode().
Fixes: c5b2d43e67bb ("soc/tegra: fuse: Add ACPI support for Tegra194 and Tegra234") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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| 7a849d0b | 20-Dec-2023 |
Kartik <kkartik@nvidia.com> |
soc/tegra: fuse: Define tegra194_soc_attr_group for Tegra241
Tegra241 SoC data uses tegra194_soc_attr_group, which is only defined if config CONFIG_ARCH_TEGRA_194_SOC or CONFIG_ARCH_TEGRA_234_SOC or
soc/tegra: fuse: Define tegra194_soc_attr_group for Tegra241
Tegra241 SoC data uses tegra194_soc_attr_group, which is only defined if config CONFIG_ARCH_TEGRA_194_SOC or CONFIG_ARCH_TEGRA_234_SOC or both are enabled. This causes a build failure if both of these configs are disabled and CONFIG_ARCH_TEGRA_241_SOC is enabled.
Define tegra194_soc_attr_group if CONFIG_ARCH_TEGRA_241_SOC is enabled.
Signed-off-by: Kartik <kkartik@nvidia.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Signed-off-by: Thierry Reding <treding@nvidia.com>
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| 972167c6 | 17-Oct-2023 |
Kartik <kkartik@nvidia.com> |
soc/tegra: fuse: Add ACPI support for Tegra194 and Tegra234
Add ACPI support for Tegra194 & Tegra243 SoC's. This requires following modifications to the probe when ACPI boot is used: - Initialize s
soc/tegra: fuse: Add ACPI support for Tegra194 and Tegra234
Add ACPI support for Tegra194 & Tegra243 SoC's. This requires following modifications to the probe when ACPI boot is used: - Initialize soc data. - Add nvmem lookups. - Register soc device. - use devm_clk_get_optional() instead of devm_clk_get() to get fuse->clk, as fuse clocks are not required when using ACPI boot.
Also, drop '__init' keyword for tegra_soc_device_register() as this is also used by tegra_fuse_probe() and use dev_err_probe() wherever applicable.
Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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| 13a69354 | 17-Oct-2023 |
Kartik <kkartik@nvidia.com> |
soc/tegra: fuse: Add function to print SKU info
Add helper function tegra_fuse_print_sku_info() to print Tegra SKU information. So, it can be shared between tegra_fuse_init() and ACPI probe which is
soc/tegra: fuse: Add function to print SKU info
Add helper function tegra_fuse_print_sku_info() to print Tegra SKU information. So, it can be shared between tegra_fuse_init() and ACPI probe which is to be introduced later.
Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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| 71661c1c | 17-Oct-2023 |
Kartik <kkartik@nvidia.com> |
soc/tegra: fuse: Add function to add lookups
Add helper function tegra_fuse_add_lookups() to register Tegra fuse nvmem lookups. So, this can be shared between tegra_fuse_init() and ACPI probe, which
soc/tegra: fuse: Add function to add lookups
Add helper function tegra_fuse_add_lookups() to register Tegra fuse nvmem lookups. So, this can be shared between tegra_fuse_init() and ACPI probe, which is to be introduced later.
Use kmemdup_array to duplicate fuse->soc->lookups.
Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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