Merge branch 'next' into for-linus

Prepare input updates for 6.6 merge window.

Merge drm/drm-next into drm-intel-next

Catching-up with drm-next and drm-intel-gt-next.
It will unblock a code refactor around the platform
definitions (names vs acronyms).

Signed-off-by: Rodrigo V

Merge drm/drm-next into drm-intel-next

Catching-up with drm-next and drm-intel-gt-next.
It will unblock a code refactor around the platform
definitions (names vs acronyms).

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

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Merge drm/drm-next into drm-intel-gt-next

Need to pull in b3e4aae612ec ("drm/i915/hdcp: Modify hdcp_gsc_message msg sending mechanism") as
a dependency for https://patchwork.freedesktop.org/series/1

Merge drm/drm-next into drm-intel-gt-next

Need to pull in b3e4aae612ec ("drm/i915/hdcp: Modify hdcp_gsc_message msg sending mechanism") as
a dependency for https://patchwork.freedesktop.org/series/121735/

Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

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Merge drm/drm-next into drm-misc-next

Backmerging to get v6.5-rc2.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>

Merge tag 'v6.4' into next

Sync up with mainline to bring in updates to shared infrastructure.

ASoC: Merge v6.5-rc2

Get a similar baseline to my other branches, and fixes for people using
the branch.

phy: cadence: Sierra: Add single link SGMII register configuration

Add single link SGMII register configuration for no SSC for
cdns,sierra-phy-t0 compatibility string.
The configuration is based on

phy: cadence: Sierra: Add single link SGMII register configuration

Add single link SGMII register configuration for no SSC for
cdns,sierra-phy-t0 compatibility string.
The configuration is based on Sierra Programmer's Guide and
validated in Cisco CrayAR SoC.

Co-developed-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
Signed-off-by: Marcin Wierzbicki <mawierzb@cisco.com>
Link: https://lore.kernel.org/r/20230626105533.2999966-1-mawierzb@cisco.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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Merge v6.5-rc1 into drm-misc-fixes

Boris needs 6.5-rc1 in drm-misc-fixes to prevent a conflict.

Signed-off-by: Maxime Ripard <mripard@kernel.org>

Merge branch 'master' into mm-hotfixes-stable

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"This batch of clk driver updates contains almost no new SoC support.
Inst

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"This batch of clk driver updates contains almost no new SoC support.
Instead there's a treewide patch series from Maxime that makes
clk_ops::determine_rate mandatory for muxes.

Beyond that core framework change we have the usual pile of clk driver
updates such as migrating i2c drivers to use .probe() again or
YAMLfication of clk DT bindings so we can validate DTBs.

Overall the SoCs that got the most updates this time around in terms
of diffstat are the Amlogic and Mediatek drivers because they added
new SoC support or fixed up various drivers to have proper data.

In general things look kinda quiet. I suspect the core framework
change may still shake out some problems after the merge window,
mostly because not everyone tests linux-next where that series has
been for some number of weeks. I saw that there's at least one pending
fix for Tegra that needs to be wrapped up into a proper patch. I'll
try to catch those bits before the window closes so that -rc1 is
bootable. More details below.

Core:
- Make clk_ops::determine_rate mandatory for muxes

New Drivers:
- Add amlogic a1 SoC family PLL and peripheral clock controller support

Updates:
- Handle allocation failures from kasprintf() and friends
- Migrate platform clk drivers to .remove_new()
- Migrate i2c clk drivers to .probe() instead of .probe_new()
- Remove CLK_SET_PARENT from all Mediatek MSDC core clocks
- Add infra_ao reset support for Mediatek MT8188 SoCs
- Align driver_data to i2c_device_id tables in some i2c clk drivers
- Use device_get_match_data() in vc5 clk driver
- New Kconfig symbol name (SOC_MICROCHIP_POLARFIRE) for Microchip
FPGA clock drivers
- Use of_property_read_bool() to read "microchip,pic32mzda-sosc"
boolean DT property in clk-pic32mzda
- Convert AT91 clock dt-bindings to YAML
- Remove CLK_SET_RATE_PARENT flag from LDB clocks on i.MX6SX
- Keep i.MX UART clocks enabled during kernel boot if earlycon is set
- Drop imx_unregister_clocks() as there are no users anymore
- Switch to _safe iterator on imx_clk_scu_unregister() to avoid use
after free
- Add determine_rate op to the imx8m composite clock
- Use device managed API for iomap and kzalloc for i.MXRT1050,
i.MX8MN, i.MX8MP and i.MX93 clock controller drivers
- Add missing interrupt DT property for the i.MX8M clock controller
- Re-add support for Exynos4212 clock controller because we are
re-introducing the SoC in the mainline
- Add CONFIG_OF dependency to Samsung clk Kconfig symbols to solve
some objtool warnings
- Preselect PLL MIPI as TCON0 parent for Allwinner A64 SoC
- Convert the Renesas clock drivers to readl_poll_timeout_atomic()
- Add PWM clock on Renesas R-Car V3U
- Fix PLL5 on Renesas RZ/G2L and RZ/V2L"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (149 commits)
clk: fix typo in clk_hw_register_fixed_rate_parent_data() macro
clk: Fix memory leak in devm_clk_notifier_register()
clk: mvebu: Iterate over possible CPUs instead of DT CPU nodes
clk: mvebu: Use of_get_cpu_hwid() to read CPU ID
MAINTAINERS: Add Marvell mvebu clock drivers
clk: clocking-wizard: check return value of devm_kasprintf()
clk: ti: clkctrl: check return value of kasprintf()
clk: keystone: sci-clk: check return value of kasprintf()
clk: si5341: free unused memory on probe failure
clk: si5341: check return value of {devm_}kasprintf()
clk: si5341: return error if one synth clock registration fails
clk: cdce925: check return value of kasprintf()
clk: vc5: check memory returned by kasprintf()
clk: mediatek: clk-mt8173-apmixedsys: Fix iomap not released issue
clk: mediatek: clk-mt8173-apmixedsys: Fix return value for of_iomap() error
clk: mediatek: clk-mtk: Grab iomem pointer for divider clocks
clk: keystone: syscon-clk: Add support for audio refclk
dt-bindings: clock: Add binding documentation for TI Audio REFCLK
dt-bindings: clock: ehrpwm: Remove unneeded syscon compatible
clk: keystone: syscon-clk: Allow the clock node to not be of type syscon
...

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Merge branch 'for-6.5/apple' into for-linus

- improved support for Keychron K8 keyboard (Lasse Brun)

Merge branches 'clk-renesas', 'clk-determine-rate', 'clk-allwinner', 'clk-samsung' and 'clk-amlogic' into clk-next

- Make clk_ops::determine_rate mandatory for muxes

* clk-renesas:
clk: renesas:

Merge branches 'clk-renesas', 'clk-determine-rate', 'clk-allwinner', 'clk-samsung' and 'clk-amlogic' into clk-next

- Make clk_ops::determine_rate mandatory for muxes

* clk-renesas:
clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic()
clk: renesas: mstp: Convert to readl_poll_timeout_atomic()
clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic()
iopoll: Do not use timekeeping in read_poll_timeout_atomic()
iopoll: Call cpu_relax() in busy loops
clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write
clk: renesas: r8a779a0: Add PWM clock

* clk-determine-rate: (71 commits)
clk: sprd: composite: Simplify determine_rate implementation
ASoC: tlv320aic32x4: pll: Remove impossible condition in clk_aic32x4_pll_determine_rate()
clk: Fix best_parent_rate after moving code into a separate function
clk: Forbid to register a mux without determine_rate
ASoC: tlv320aic32x4: div: Switch to determine_rate
ASoC: tlv320aic32x4: pll: Switch to determine_rate
clk: tegra: super: Switch to determine_rate
clk: tegra: periph: Switch to determine_rate
clk: stm32: composite: Switch to determine_rate
clk: st: flexgen: Switch to determine_rate
clk: sprd: composite: Switch to determine_rate
clk: ingenic: tcu: Switch to determine_rate
clk: ingenic: cgu: Switch to determine_rate
clk: imx: scu: Switch to determine_rate
clk: da8xx: clk48: Switch to determine_rate
clk: si5351: clkout: Switch to determine_rate
clk: si5351: msynth: Switch to determine_rate
clk: si5351: pll: Switch to determine_rate
clk: si5341: Switch to determine_rate
clk: cdce706: clkout: Switch to determine_rate
...

* clk-allwinner:
clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux

* clk-samsung:
clk: samsung: add CONFIG_OF dependency
clk: samsung: Re-add support for Exynos4212 CPU clock
clk: samsung: Add Exynos4212 compatible to CLKOUT driver
dt-bindings: clock: samsung,exynos: add Exynos4212 clock compatible

* clk-amlogic:
MAINTAINERS: repair pattern in ARM/Amlogic Meson SoC CLOCK FRAMEWORK
clk: meson: pll: remove unneeded semicolon
clk: meson: a1: Staticize rtc clk
clk: meson: a1: add Amlogic A1 Peripherals clock controller driver
clk: meson: a1: add Amlogic A1 PLL clock controller driver
clk: meson: introduce new pll power-on sequence for A1 SoC family
clk: meson: make pll rst bit as optional
dt-bindings: clock: meson: add A1 Peripherals clock controller bindings
dt-bindings: clock: meson: add A1 PLL clock controller bindings

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Merge drm/drm-next into drm-misc-next-fixes

Backmerging to sync drm-misc-next-fixes with drm-misc-next.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>

Merge branch 'drm-next' of git://anongit.freedesktop.org/drm/drm into msm-next-lumag-base

Merge the drm-next tree to pick up the DRM DSC helpers (merged via
drm-intel-next tree). MSM DSC v1.2 patche

Merge branch 'drm-next' of git://anongit.freedesktop.org/drm/drm into msm-next-lumag-base

Merge the drm-next tree to pick up the DRM DSC helpers (merged via
drm-intel-next tree). MSM DSC v1.2 patches depend on these helpers.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

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phy: cadence: sierra: Add a determine_rate hook

The Cadence Sierra PLL clock implements a mux with a set_parent hook,
but doesn't provide a determine_rate implementation.

This is a bit odd, since s

phy: cadence: sierra: Add a determine_rate hook

The Cadence Sierra PLL clock implements a mux with a set_parent hook,
but doesn't provide a determine_rate implementation.

This is a bit odd, since set_parent() is there to, as its name implies,
change the parent of a clock. However, the most likely candidate to
trigger that parent change is a call to clk_set_rate(), with
determine_rate() figuring out which parent is the best suited for a
given rate.

The other trigger would be a call to clk_set_parent(), but it's far less
used, and it doesn't look like there's any obvious user for that clock.

So, the set_parent hook is effectively unused, possibly because of an
oversight. However, it could also be an explicit decision by the
original author to avoid any reparenting but through an explicit call to
clk_set_parent().

The latter case would be equivalent to setting the flag
CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook
to __clk_mux_determine_rate(). Indeed, if no determine_rate
implementation is provided, clk_round_rate() (through
clk_core_round_rate_nolock()) will call itself on the parent if
CLK_SET_RATE_PARENT is set, and will not change the clock rate
otherwise.

And if it was an oversight, then we are at least explicit about our
behavior now and it can be further refined down the line.

Since the CLK_SET_RATE_NO_REPARENT flag was already set though, it seems
unlikely.

Cc: Kishon Vijay Abraham I <kishon@kernel.org>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: linux-phy@lists.infradead.org
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-41-971d5077e7d2@cerno.tech
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Merge tag 'v6.4-rc4' into wpan-next/staging

Linux 6.4-rc4

Merge drm/drm-next into drm-intel-gt-next

For conflict avoidance we need the following commit:

c9a9f18d3ad8 drm/i915/huc: use const struct bus_type pointers

Signed-off-by: Tvrtko Ursulin <tvrtko

Merge drm/drm-next into drm-intel-gt-next

For conflict avoidance we need the following commit:

c9a9f18d3ad8 drm/i915/huc: use const struct bus_type pointers

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

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Merge drm/drm-next into drm-intel-next

Backmerge to get some hwmon dependencies.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Merge drm/drm-fixes into drm-misc-fixes

Let's bring 6.4-rc1 in drm-misc-fixes to start the new fix cycle.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>

Merge drm/drm-next into drm-misc-next

Start the 6.5 release cycle.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>

Merge tag 'phy-for-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

Pull phy updates from Vinod Koul:
"New support:
- UFS PHY for Qualcomm SA8775p, SM7150
- PCIe 2 lane phy

Merge tag 'phy-for-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

Pull phy updates from Vinod Koul:
"New support:
- UFS PHY for Qualcomm SA8775p, SM7150
- PCIe 2 lane phy support for sc8180x and PCIe PHY for SDX65
- Mediatke hdmi phy support for mt8195
- rockchip naneng combo phy support for RK358

Updates:
- Drop Thunder Bay eMMC PHY driver
- RC support for PCIe phy for Qualcomm SDX55
- SGMII support in WIZ driver for J721E
- PCIe and multilink SGMII PHY support in cadence driver
- Big pile of platform remove callback returning void conversions"

* tag 'phy-for-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (77 commits)
phy: cadence: cdns-dphy-rx: Add common module reset support
phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J721E
dt-bindings: phy: ti: phy-gmii-sel: Add support for J784S4 CPSW9G
phy: ti: j721e-wiz: Fix unreachable code in wiz_mode_select()
phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration
phy: mediatek: add support for phy-mtk-hdmi-mt8195
phy: phy-mtk-hdmi: Add generic phy configure callback
dt-bindings: phy: mediatek: hdmi-phy: Add mt8195 compatible
phy: tegra: xusb: Add missing tegra_xusb_port_unregister for usb2_port and ulpi_port
dt-bindings: phy: ti,phy-j721e-wiz: document clock-output-names
dt-bindings: phy: ti,phy-j721e-wiz: drop assigned-clocks
dt-bindings: phy: ti,phy-am654-serdes: drop assigned-clocks type
dt-bindings: phy: cadence-torrent: drop assigned-clocks
dt-bindings: phy: cadence-sierra: drop assigned-clocks
phy: rockchip: remove unused hw_to_inno function
phy: qualcomm: phy-qcom-qmp-ufs: add definitions for sa8775p
dt-bindings: phy: qmp-ufs: describe the UFS PHY for sa8775p
phy: qcom-qmp-pcie: drop sdm845_qhp_pcie_rx_tbl
phy: qcom-qmp-pcie: sc8180x PCIe PHY has 2 lanes
phy: qcom-qmp-ufs: Add SM7150 support
...

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phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration

Add register sequences for PCIe + SGMII PHY multilink configuration.
This has been validated on TI J7 platforms.

Signed-off-by: Sw

phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration

Add register sequences for PCIe + SGMII PHY multilink configuration.
This has been validated on TI J7 platforms.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230403085644.10187-1-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: cadence: Sierra: Use clk_parent_data to provide parent information

Rather than requesting the parent reference clocks for the sierra PHY PLLs
and then assigning the parents as a struct clk. Use

phy: cadence: Sierra: Use clk_parent_data to provide parent information

Rather than requesting the parent reference clocks for the sierra PHY PLLs
and then assigning the parents as a struct clk. Use the clk_parent_data
feature for the clock framework and only specify the firmware names of the
parent clocks.

The clock framework internally will then translate this to the actual
clocks. This allows to remove a bit of boilerplate code.

It also allows to only specify a single reference clock for both PLLs,
which is a valid use case. The clock framework can handle the case where
not all inputs for a clock mux are connected, while the custom
implementation in the driver could not.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Link: https://lore.kernel.org/r/20230326011416.363318-2-lars@metafoo.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: cadence: Sierra: Replace `clk_register(`) with `clk_hw_register()`

The `devm_clk_register()` API is deprecated. Switch to
`devm_clk_hw_register()`.

Since the driver enables its own internal PL

phy: cadence: Sierra: Replace `clk_register(`) with `clk_hw_register()`

The `devm_clk_register()` API is deprecated. Switch to
`devm_clk_hw_register()`.

Since the driver enables its own internal PLLs using the clock API we
still need to get a reference to the PLL clocks using the
`devm_clk_hw_get_clk()` API.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Link: https://lore.kernel.org/r/20230326011416.363318-1-lars@metafoo.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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phy: cadence: phy-cadence-sierra: Convert to platform remove callback returning void

The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's p

phy: cadence: phy-cadence-sierra: Convert to platform remove callback returning void

The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.

Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20230307115900.2293120-5-u.kleine-koenig@pengutronix.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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