1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Cadence Sierra PHY Driver 4 * 5 * Copyright (c) 2018 Cadence Design Systems 6 * Author: Alan Douglas <adouglas@cadence.com> 7 * 8 */ 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/phy/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <linux/reset.h> 20 #include <linux/slab.h> 21 #include <linux/of.h> 22 #include <linux/of_platform.h> 23 #include <dt-bindings/phy/phy.h> 24 #include <dt-bindings/phy/phy-cadence.h> 25 26 #define NUM_SSC_MODE 3 27 #define NUM_PHY_TYPE 5 28 29 /* PHY register offsets */ 30 #define SIERRA_COMMON_CDB_OFFSET 0x0 31 #define SIERRA_MACRO_ID_REG 0x0 32 #define SIERRA_CMN_PLLLC_GEN_PREG 0x42 33 #define SIERRA_CMN_PLLLC_MODE_PREG 0x48 34 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49 35 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A 36 #define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG 0x4B 37 #define SIERRA_CMN_PLLLC_CLK1_PREG 0x4D 38 #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F 39 #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50 40 #define SIERRA_CMN_PLLLC_DSMCORR_PREG 0x51 41 #define SIERRA_CMN_PLLLC_SS_PREG 0x52 42 #define SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG 0x53 43 #define SIERRA_CMN_PLLLC_SSTWOPT_PREG 0x54 44 #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 45 #define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG 0x63 46 #define SIERRA_CMN_REFRCV_PREG 0x98 47 #define SIERRA_CMN_REFRCV1_PREG 0xB8 48 #define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2 49 #define SIERRA_CMN_PLLLC1_FBDIV_INT_PREG 0xC3 50 #define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG 0xCA 51 #define SIERRA_CMN_PLLLC1_CLK0_PREG 0xCE 52 #define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG 0xD0 53 #define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG 0xE2 54 55 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 56 ((0x4000 << (block_offset)) + \ 57 (((ln) << 9) << (reg_offset))) 58 59 #define SIERRA_DET_STANDEC_A_PREG 0x000 60 #define SIERRA_DET_STANDEC_B_PREG 0x001 61 #define SIERRA_DET_STANDEC_C_PREG 0x002 62 #define SIERRA_DET_STANDEC_D_PREG 0x003 63 #define SIERRA_DET_STANDEC_E_PREG 0x004 64 #define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008 65 #define SIERRA_PSM_A0IN_TMR_PREG 0x009 66 #define SIERRA_PSM_A3IN_TMR_PREG 0x00C 67 #define SIERRA_PSM_DIAG_PREG 0x015 68 #define SIERRA_PSC_LN_A3_PREG 0x023 69 #define SIERRA_PSC_LN_A4_PREG 0x024 70 #define SIERRA_PSC_LN_IDLE_PREG 0x026 71 #define SIERRA_PSC_TX_A0_PREG 0x028 72 #define SIERRA_PSC_TX_A1_PREG 0x029 73 #define SIERRA_PSC_TX_A2_PREG 0x02A 74 #define SIERRA_PSC_TX_A3_PREG 0x02B 75 #define SIERRA_PSC_RX_A0_PREG 0x030 76 #define SIERRA_PSC_RX_A1_PREG 0x031 77 #define SIERRA_PSC_RX_A2_PREG 0x032 78 #define SIERRA_PSC_RX_A3_PREG 0x033 79 #define SIERRA_PLLCTRL_FBDIV_MODE01_PREG 0x039 80 #define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A 81 #define SIERRA_PLLCTRL_GEN_A_PREG 0x03B 82 #define SIERRA_PLLCTRL_GEN_D_PREG 0x03E 83 #define SIERRA_PLLCTRL_CPGAIN_MODE_PREG 0x03F 84 #define SIERRA_PLLCTRL_STATUS_PREG 0x044 85 #define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B 86 #define SIERRA_DFE_BIASTRIM_PREG 0x04C 87 #define SIERRA_DRVCTRL_ATTEN_PREG 0x06A 88 #define SIERRA_DRVCTRL_BOOST_PREG 0x06F 89 #define SIERRA_TX_RCVDET_OVRD_PREG 0x072 90 #define SIERRA_CLKPATHCTRL_TMR_PREG 0x081 91 #define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085 92 #define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG 0x086 93 #define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087 94 #define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088 95 #define SIERRA_CREQ_DCBIASATTEN_OVR_PREG 0x08C 96 #define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E 97 #define SIERRA_RX_CTLE_CAL_PREG 0x08F 98 #define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091 99 #define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092 100 #define SIERRA_CREQ_EQ_CTRL_PREG 0x093 101 #define SIERRA_CREQ_SPARE_PREG 0x096 102 #define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG 0x097 103 #define SIERRA_CTLELUT_CTRL_PREG 0x098 104 #define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0 105 #define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1 106 #define SIERRA_DEQ_PHALIGN_CTRL 0x0C4 107 #define SIERRA_DEQ_CONCUR_CTRL1_PREG 0x0C8 108 #define SIERRA_DEQ_CONCUR_CTRL2_PREG 0x0C9 109 #define SIERRA_DEQ_EPIPWR_CTRL2_PREG 0x0CD 110 #define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG 0x0CE 111 #define SIERRA_DEQ_ERRCMP_CTRL_PREG 0x0D0 112 #define SIERRA_DEQ_OFFSET_CTRL_PREG 0x0D8 113 #define SIERRA_DEQ_GAIN_CTRL_PREG 0x0E0 114 #define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1 115 #define SIERRA_DEQ_GLUT0 0x0E8 116 #define SIERRA_DEQ_GLUT1 0x0E9 117 #define SIERRA_DEQ_GLUT2 0x0EA 118 #define SIERRA_DEQ_GLUT3 0x0EB 119 #define SIERRA_DEQ_GLUT4 0x0EC 120 #define SIERRA_DEQ_GLUT5 0x0ED 121 #define SIERRA_DEQ_GLUT6 0x0EE 122 #define SIERRA_DEQ_GLUT7 0x0EF 123 #define SIERRA_DEQ_GLUT8 0x0F0 124 #define SIERRA_DEQ_GLUT9 0x0F1 125 #define SIERRA_DEQ_GLUT10 0x0F2 126 #define SIERRA_DEQ_GLUT11 0x0F3 127 #define SIERRA_DEQ_GLUT12 0x0F4 128 #define SIERRA_DEQ_GLUT13 0x0F5 129 #define SIERRA_DEQ_GLUT14 0x0F6 130 #define SIERRA_DEQ_GLUT15 0x0F7 131 #define SIERRA_DEQ_GLUT16 0x0F8 132 #define SIERRA_DEQ_ALUT0 0x108 133 #define SIERRA_DEQ_ALUT1 0x109 134 #define SIERRA_DEQ_ALUT2 0x10A 135 #define SIERRA_DEQ_ALUT3 0x10B 136 #define SIERRA_DEQ_ALUT4 0x10C 137 #define SIERRA_DEQ_ALUT5 0x10D 138 #define SIERRA_DEQ_ALUT6 0x10E 139 #define SIERRA_DEQ_ALUT7 0x10F 140 #define SIERRA_DEQ_ALUT8 0x110 141 #define SIERRA_DEQ_ALUT9 0x111 142 #define SIERRA_DEQ_ALUT10 0x112 143 #define SIERRA_DEQ_ALUT11 0x113 144 #define SIERRA_DEQ_ALUT12 0x114 145 #define SIERRA_DEQ_ALUT13 0x115 146 #define SIERRA_DEQ_DFETAP_CTRL_PREG 0x128 147 #define SIERRA_DEQ_DFETAP0 0x129 148 #define SIERRA_DEQ_DFETAP1 0x12B 149 #define SIERRA_DEQ_DFETAP2 0x12D 150 #define SIERRA_DEQ_DFETAP3 0x12F 151 #define SIERRA_DEQ_DFETAP4 0x131 152 #define SIERRA_DFE_EN_1010_IGNORE_PREG 0x134 153 #define SIERRA_DEQ_PRECUR_PREG 0x138 154 #define SIERRA_DEQ_POSTCUR_PREG 0x140 155 #define SIERRA_DEQ_POSTCUR_DECR_PREG 0x142 156 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 157 #define SIERRA_DEQ_TAU_CTRL2_PREG 0x151 158 #define SIERRA_DEQ_TAU_CTRL3_PREG 0x152 159 #define SIERRA_DEQ_OPENEYE_CTRL_PREG 0x158 160 #define SIERRA_DEQ_PICTRL_PREG 0x161 161 #define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170 162 #define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171 163 #define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174 164 #define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C 165 #define SIERRA_CPI_RESBIAS_BIN_PREG 0x17E 166 #define SIERRA_CPI_TRIM_PREG 0x17F 167 #define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG 0x183 168 #define SIERRA_EPI_CTRL_PREG 0x187 169 #define SIERRA_LFPSDET_SUPPORT_PREG 0x188 170 #define SIERRA_LFPSFILT_NS_PREG 0x18A 171 #define SIERRA_LFPSFILT_RD_PREG 0x18B 172 #define SIERRA_LFPSFILT_MP_PREG 0x18C 173 #define SIERRA_SIGDET_SUPPORT_PREG 0x190 174 #define SIERRA_SDFILT_H2L_A_PREG 0x191 175 #define SIERRA_SDFILT_L2H_PREG 0x193 176 #define SIERRA_RXBUFFER_CTLECTRL_PREG 0x19E 177 #define SIERRA_RXBUFFER_RCDFECTRL_PREG 0x19F 178 #define SIERRA_RXBUFFER_DFECTRL_PREG 0x1A0 179 #define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F 180 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 181 182 /* PHY PCS common registers */ 183 #define SIERRA_PHY_PCS_COMMON_OFFSET(block_offset) \ 184 (0xc000 << (block_offset)) 185 #define SIERRA_PHY_PIPE_CMN_CTRL1 0x0 186 #define SIERRA_PHY_PLL_CFG 0xe 187 188 /* PHY PCS lane registers */ 189 #define SIERRA_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 190 ((0xD000 << (block_offset)) + \ 191 (((ln) << 8) << (reg_offset))) 192 193 #define SIERRA_PHY_ISO_LINK_CTRL 0xB 194 195 /* PHY PMA common registers */ 196 #define SIERRA_PHY_PMA_COMMON_OFFSET(block_offset) \ 197 (0xE000 << (block_offset)) 198 #define SIERRA_PHY_PMA_CMN_CTRL 0x000 199 200 /* PHY PMA lane registers */ 201 #define SIERRA_PHY_PMA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 202 ((0xF000 << (block_offset)) + \ 203 (((ln) << 8) << (reg_offset))) 204 205 #define SIERRA_PHY_PMA_XCVR_CTRL 0x000 206 207 #define SIERRA_MACRO_ID 0x00007364 208 #define SIERRA_MAX_LANES 16 209 #define PLL_LOCK_TIME 100000 210 211 #define CDNS_SIERRA_OUTPUT_CLOCKS 3 212 #define CDNS_SIERRA_INPUT_CLOCKS 3 213 enum cdns_sierra_clock_input { 214 PHY_CLK, 215 CMN_REFCLK_DIG_DIV, 216 CMN_REFCLK1_DIG_DIV, 217 }; 218 219 #define SIERRA_NUM_CMN_PLLC 2 220 #define SIERRA_NUM_CMN_PLLC_PARENTS 2 221 222 static const struct reg_field macro_id_type = 223 REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); 224 static const struct reg_field phy_pll_cfg_1 = 225 REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1); 226 static const struct reg_field pma_cmn_ready = 227 REG_FIELD(SIERRA_PHY_PMA_CMN_CTRL, 0, 0); 228 static const struct reg_field pllctrl_lock = 229 REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0); 230 static const struct reg_field phy_iso_link_ctrl_1 = 231 REG_FIELD(SIERRA_PHY_ISO_LINK_CTRL, 1, 1); 232 static const struct reg_field cmn_plllc_clk1outdiv_preg = 233 REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 0, 6); 234 static const struct reg_field cmn_plllc_clk1_en_preg = 235 REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 12, 12); 236 237 static const char * const clk_names[] = { 238 [CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc", 239 [CDNS_SIERRA_PLL_CMNLC1] = "pll_cmnlc1", 240 [CDNS_SIERRA_DERIVED_REFCLK] = "refclk_der", 241 }; 242 243 enum cdns_sierra_cmn_plllc { 244 CMN_PLLLC, 245 CMN_PLLLC1, 246 }; 247 248 struct cdns_sierra_pll_mux_reg_fields { 249 struct reg_field pfdclk_sel_preg; 250 struct reg_field plllc1en_field; 251 struct reg_field termen_field; 252 }; 253 254 static const struct cdns_sierra_pll_mux_reg_fields cmn_plllc_pfdclk1_sel_preg[] = { 255 [CMN_PLLLC] = { 256 .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1), 257 .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8), 258 .termen_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0), 259 }, 260 [CMN_PLLLC1] = { 261 .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1), 262 .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8), 263 .termen_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0), 264 }, 265 }; 266 267 struct cdns_sierra_pll_mux { 268 struct clk_hw hw; 269 struct regmap_field *pfdclk_sel_preg; 270 struct regmap_field *plllc1en_field; 271 struct regmap_field *termen_field; 272 struct clk_init_data clk_data; 273 }; 274 275 #define to_cdns_sierra_pll_mux(_hw) \ 276 container_of(_hw, struct cdns_sierra_pll_mux, hw) 277 278 #define PLL0_REFCLK_NAME "pll0_refclk" 279 #define PLL1_REFCLK_NAME "pll1_refclk" 280 281 static const struct clk_parent_data pll_mux_parent_data[][SIERRA_NUM_CMN_PLLC_PARENTS] = { 282 [CMN_PLLLC] = { 283 { .fw_name = PLL0_REFCLK_NAME }, 284 { .fw_name = PLL1_REFCLK_NAME } 285 }, 286 [CMN_PLLLC1] = { 287 { .fw_name = PLL1_REFCLK_NAME }, 288 { .fw_name = PLL0_REFCLK_NAME } 289 }, 290 }; 291 292 static u32 cdns_sierra_pll_mux_table[][SIERRA_NUM_CMN_PLLC_PARENTS] = { 293 [CMN_PLLLC] = { 0, 1 }, 294 [CMN_PLLLC1] = { 1, 0 }, 295 }; 296 297 struct cdns_sierra_derived_refclk { 298 struct clk_hw hw; 299 struct regmap_field *cmn_plllc_clk1outdiv_preg; 300 struct regmap_field *cmn_plllc_clk1_en_preg; 301 struct clk_init_data clk_data; 302 }; 303 304 #define to_cdns_sierra_derived_refclk(_hw) \ 305 container_of(_hw, struct cdns_sierra_derived_refclk, hw) 306 307 enum cdns_sierra_phy_type { 308 TYPE_NONE, 309 TYPE_PCIE, 310 TYPE_USB, 311 TYPE_SGMII, 312 TYPE_QSGMII 313 }; 314 315 enum cdns_sierra_ssc_mode { 316 NO_SSC, 317 EXTERNAL_SSC, 318 INTERNAL_SSC 319 }; 320 321 struct cdns_sierra_inst { 322 struct phy *phy; 323 enum cdns_sierra_phy_type phy_type; 324 u32 num_lanes; 325 u32 mlane; 326 struct reset_control *lnk_rst; 327 enum cdns_sierra_ssc_mode ssc_mode; 328 }; 329 330 struct cdns_reg_pairs { 331 u16 val; 332 u32 off; 333 }; 334 335 struct cdns_sierra_vals { 336 const struct cdns_reg_pairs *reg_pairs; 337 u32 num_regs; 338 }; 339 340 struct cdns_sierra_data { 341 u32 id_value; 342 u8 block_offset_shift; 343 u8 reg_offset_shift; 344 struct cdns_sierra_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 345 [NUM_SSC_MODE]; 346 struct cdns_sierra_vals *phy_pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 347 [NUM_SSC_MODE]; 348 struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 349 [NUM_SSC_MODE]; 350 struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 351 [NUM_SSC_MODE]; 352 }; 353 354 struct cdns_regmap_cdb_context { 355 struct device *dev; 356 void __iomem *base; 357 u8 reg_offset_shift; 358 }; 359 360 struct cdns_sierra_phy { 361 struct device *dev; 362 const struct cdns_sierra_data *init_data; 363 struct cdns_sierra_inst phys[SIERRA_MAX_LANES]; 364 struct reset_control *phy_rst; 365 struct reset_control *apb_rst; 366 struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES]; 367 struct regmap *regmap_phy_pcs_common_cdb; 368 struct regmap *regmap_phy_pcs_lane_cdb[SIERRA_MAX_LANES]; 369 struct regmap *regmap_phy_pma_common_cdb; 370 struct regmap *regmap_phy_pma_lane_cdb[SIERRA_MAX_LANES]; 371 struct regmap *regmap_common_cdb; 372 struct regmap_field *macro_id_type; 373 struct regmap_field *phy_pll_cfg_1; 374 struct regmap_field *pma_cmn_ready; 375 struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; 376 struct regmap_field *phy_iso_link_ctrl_1[SIERRA_MAX_LANES]; 377 struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC]; 378 struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC]; 379 struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC]; 380 struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS]; 381 int nsubnodes; 382 u32 num_lanes; 383 bool autoconf; 384 int already_configured; 385 struct clk *pll_clks[SIERRA_NUM_CMN_PLLC]; 386 struct clk_hw_onecell_data clk_data; 387 }; 388 389 static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) 390 { 391 struct cdns_regmap_cdb_context *ctx = context; 392 u32 offset = reg << ctx->reg_offset_shift; 393 394 writew(val, ctx->base + offset); 395 396 return 0; 397 } 398 399 static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) 400 { 401 struct cdns_regmap_cdb_context *ctx = context; 402 u32 offset = reg << ctx->reg_offset_shift; 403 404 *val = readw(ctx->base + offset); 405 return 0; 406 } 407 408 #define SIERRA_LANE_CDB_REGMAP_CONF(n) \ 409 { \ 410 .name = "sierra_lane" n "_cdb", \ 411 .reg_stride = 1, \ 412 .fast_io = true, \ 413 .reg_write = cdns_regmap_write, \ 414 .reg_read = cdns_regmap_read, \ 415 } 416 417 static const struct regmap_config cdns_sierra_lane_cdb_config[] = { 418 SIERRA_LANE_CDB_REGMAP_CONF("0"), 419 SIERRA_LANE_CDB_REGMAP_CONF("1"), 420 SIERRA_LANE_CDB_REGMAP_CONF("2"), 421 SIERRA_LANE_CDB_REGMAP_CONF("3"), 422 SIERRA_LANE_CDB_REGMAP_CONF("4"), 423 SIERRA_LANE_CDB_REGMAP_CONF("5"), 424 SIERRA_LANE_CDB_REGMAP_CONF("6"), 425 SIERRA_LANE_CDB_REGMAP_CONF("7"), 426 SIERRA_LANE_CDB_REGMAP_CONF("8"), 427 SIERRA_LANE_CDB_REGMAP_CONF("9"), 428 SIERRA_LANE_CDB_REGMAP_CONF("10"), 429 SIERRA_LANE_CDB_REGMAP_CONF("11"), 430 SIERRA_LANE_CDB_REGMAP_CONF("12"), 431 SIERRA_LANE_CDB_REGMAP_CONF("13"), 432 SIERRA_LANE_CDB_REGMAP_CONF("14"), 433 SIERRA_LANE_CDB_REGMAP_CONF("15"), 434 }; 435 436 static const struct regmap_config cdns_sierra_common_cdb_config = { 437 .name = "sierra_common_cdb", 438 .reg_stride = 1, 439 .fast_io = true, 440 .reg_write = cdns_regmap_write, 441 .reg_read = cdns_regmap_read, 442 }; 443 444 static const struct regmap_config cdns_sierra_phy_pcs_cmn_cdb_config = { 445 .name = "sierra_phy_pcs_cmn_cdb", 446 .reg_stride = 1, 447 .fast_io = true, 448 .reg_write = cdns_regmap_write, 449 .reg_read = cdns_regmap_read, 450 }; 451 452 #define SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \ 453 { \ 454 .name = "sierra_phy_pcs_lane" n "_cdb", \ 455 .reg_stride = 1, \ 456 .fast_io = true, \ 457 .reg_write = cdns_regmap_write, \ 458 .reg_read = cdns_regmap_read, \ 459 } 460 461 static const struct regmap_config cdns_sierra_phy_pcs_lane_cdb_config[] = { 462 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("0"), 463 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("1"), 464 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("2"), 465 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("3"), 466 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("4"), 467 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("5"), 468 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("6"), 469 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("7"), 470 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("8"), 471 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("9"), 472 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("10"), 473 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("11"), 474 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("12"), 475 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("13"), 476 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("14"), 477 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("15"), 478 }; 479 480 static const struct regmap_config cdns_sierra_phy_pma_cmn_cdb_config = { 481 .name = "sierra_phy_pma_cmn_cdb", 482 .reg_stride = 1, 483 .fast_io = true, 484 .reg_write = cdns_regmap_write, 485 .reg_read = cdns_regmap_read, 486 }; 487 488 #define SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF(n) \ 489 { \ 490 .name = "sierra_phy_pma_lane" n "_cdb", \ 491 .reg_stride = 1, \ 492 .fast_io = true, \ 493 .reg_write = cdns_regmap_write, \ 494 .reg_read = cdns_regmap_read, \ 495 } 496 497 static const struct regmap_config cdns_sierra_phy_pma_lane_cdb_config[] = { 498 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("0"), 499 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("1"), 500 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("2"), 501 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("3"), 502 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("4"), 503 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("5"), 504 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("6"), 505 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("7"), 506 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("8"), 507 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("9"), 508 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("10"), 509 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("11"), 510 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("12"), 511 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("13"), 512 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("14"), 513 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("15"), 514 }; 515 516 static int cdns_sierra_phy_init(struct phy *gphy) 517 { 518 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 519 struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent); 520 const struct cdns_sierra_data *init_data = phy->init_data; 521 struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals; 522 enum cdns_sierra_phy_type phy_type = ins->phy_type; 523 enum cdns_sierra_ssc_mode ssc = ins->ssc_mode; 524 struct cdns_sierra_vals *phy_pma_ln_vals; 525 const struct cdns_reg_pairs *reg_pairs; 526 struct cdns_sierra_vals *pcs_cmn_vals; 527 struct regmap *regmap; 528 u32 num_regs; 529 int i, j; 530 531 /* Initialise the PHY registers, unless auto configured */ 532 if (phy->autoconf || phy->already_configured || phy->nsubnodes > 1) 533 return 0; 534 535 clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000); 536 clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); 537 538 /* PHY PCS common registers configurations */ 539 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc]; 540 if (pcs_cmn_vals) { 541 reg_pairs = pcs_cmn_vals->reg_pairs; 542 num_regs = pcs_cmn_vals->num_regs; 543 regmap = phy->regmap_phy_pcs_common_cdb; 544 for (i = 0; i < num_regs; i++) 545 regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); 546 } 547 548 /* PHY PMA lane registers configurations */ 549 phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_type][TYPE_NONE][ssc]; 550 if (phy_pma_ln_vals) { 551 reg_pairs = phy_pma_ln_vals->reg_pairs; 552 num_regs = phy_pma_ln_vals->num_regs; 553 for (i = 0; i < ins->num_lanes; i++) { 554 regmap = phy->regmap_phy_pma_lane_cdb[i + ins->mlane]; 555 for (j = 0; j < num_regs; j++) 556 regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val); 557 } 558 } 559 560 /* PMA common registers configurations */ 561 pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc]; 562 if (pma_cmn_vals) { 563 reg_pairs = pma_cmn_vals->reg_pairs; 564 num_regs = pma_cmn_vals->num_regs; 565 regmap = phy->regmap_common_cdb; 566 for (i = 0; i < num_regs; i++) 567 regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); 568 } 569 570 /* PMA lane registers configurations */ 571 pma_ln_vals = init_data->pma_ln_vals[phy_type][TYPE_NONE][ssc]; 572 if (pma_ln_vals) { 573 reg_pairs = pma_ln_vals->reg_pairs; 574 num_regs = pma_ln_vals->num_regs; 575 for (i = 0; i < ins->num_lanes; i++) { 576 regmap = phy->regmap_lane_cdb[i + ins->mlane]; 577 for (j = 0; j < num_regs; j++) 578 regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val); 579 } 580 } 581 582 return 0; 583 } 584 585 static int cdns_sierra_phy_on(struct phy *gphy) 586 { 587 struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent); 588 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 589 struct device *dev = sp->dev; 590 u32 val; 591 int ret; 592 593 if (sp->nsubnodes == 1) { 594 /* Take the PHY out of reset */ 595 ret = reset_control_deassert(sp->phy_rst); 596 if (ret) { 597 dev_err(dev, "Failed to take the PHY out of reset\n"); 598 return ret; 599 } 600 } 601 602 /* Take the PHY lane group out of reset */ 603 ret = reset_control_deassert(ins->lnk_rst); 604 if (ret) { 605 dev_err(dev, "Failed to take the PHY lane out of reset\n"); 606 return ret; 607 } 608 609 if (ins->phy_type == TYPE_PCIE || ins->phy_type == TYPE_USB) { 610 ret = regmap_field_read_poll_timeout(sp->phy_iso_link_ctrl_1[ins->mlane], 611 val, !val, 1000, PLL_LOCK_TIME); 612 if (ret) { 613 dev_err(dev, "Timeout waiting for PHY status ready\n"); 614 return ret; 615 } 616 } 617 618 /* 619 * Wait for cmn_ready assertion 620 * PHY_PMA_CMN_CTRL[0] == 1 621 */ 622 ret = regmap_field_read_poll_timeout(sp->pma_cmn_ready, val, val, 623 1000, PLL_LOCK_TIME); 624 if (ret) { 625 dev_err(dev, "Timeout waiting for CMN ready\n"); 626 return ret; 627 } 628 629 ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane], 630 val, val, 1000, PLL_LOCK_TIME); 631 if (ret < 0) 632 dev_err(dev, "PLL lock of lane failed\n"); 633 634 return ret; 635 } 636 637 static int cdns_sierra_phy_off(struct phy *gphy) 638 { 639 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 640 641 return reset_control_assert(ins->lnk_rst); 642 } 643 644 static int cdns_sierra_phy_reset(struct phy *gphy) 645 { 646 struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent); 647 648 reset_control_assert(sp->phy_rst); 649 reset_control_deassert(sp->phy_rst); 650 return 0; 651 }; 652 653 static const struct phy_ops ops = { 654 .init = cdns_sierra_phy_init, 655 .power_on = cdns_sierra_phy_on, 656 .power_off = cdns_sierra_phy_off, 657 .reset = cdns_sierra_phy_reset, 658 .owner = THIS_MODULE, 659 }; 660 661 static int cdns_sierra_noop_phy_on(struct phy *gphy) 662 { 663 usleep_range(5000, 10000); 664 665 return 0; 666 } 667 668 static const struct phy_ops noop_ops = { 669 .power_on = cdns_sierra_noop_phy_on, 670 .owner = THIS_MODULE, 671 }; 672 673 static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw) 674 { 675 struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw); 676 struct regmap_field *plllc1en_field = mux->plllc1en_field; 677 struct regmap_field *termen_field = mux->termen_field; 678 struct regmap_field *field = mux->pfdclk_sel_preg; 679 unsigned int val; 680 int index; 681 682 regmap_field_read(field, &val); 683 684 if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1])) { 685 index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC1], 0, val); 686 if (index == 1) { 687 regmap_field_write(plllc1en_field, 1); 688 regmap_field_write(termen_field, 1); 689 } 690 } else { 691 index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC], 0, val); 692 } 693 694 return index; 695 } 696 697 static int cdns_sierra_pll_mux_set_parent(struct clk_hw *hw, u8 index) 698 { 699 struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw); 700 struct regmap_field *plllc1en_field = mux->plllc1en_field; 701 struct regmap_field *termen_field = mux->termen_field; 702 struct regmap_field *field = mux->pfdclk_sel_preg; 703 int val, ret; 704 705 ret = regmap_field_write(plllc1en_field, 0); 706 ret |= regmap_field_write(termen_field, 0); 707 if (index == 1) { 708 ret |= regmap_field_write(plllc1en_field, 1); 709 ret |= regmap_field_write(termen_field, 1); 710 } 711 712 if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1])) 713 val = cdns_sierra_pll_mux_table[CMN_PLLLC1][index]; 714 else 715 val = cdns_sierra_pll_mux_table[CMN_PLLLC][index]; 716 717 ret |= regmap_field_write(field, val); 718 719 return ret; 720 } 721 722 static const struct clk_ops cdns_sierra_pll_mux_ops = { 723 .set_parent = cdns_sierra_pll_mux_set_parent, 724 .get_parent = cdns_sierra_pll_mux_get_parent, 725 }; 726 727 static int cdns_sierra_pll_mux_register(struct cdns_sierra_phy *sp, 728 struct regmap_field *pfdclk1_sel_field, 729 struct regmap_field *plllc1en_field, 730 struct regmap_field *termen_field, 731 int clk_index) 732 { 733 struct cdns_sierra_pll_mux *mux; 734 struct device *dev = sp->dev; 735 struct clk_init_data *init; 736 char clk_name[100]; 737 int ret; 738 739 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 740 if (!mux) 741 return -ENOMEM; 742 743 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), clk_names[clk_index]); 744 745 init = &mux->clk_data; 746 747 init->ops = &cdns_sierra_pll_mux_ops; 748 init->flags = CLK_SET_RATE_NO_REPARENT; 749 init->parent_data = pll_mux_parent_data[clk_index]; 750 init->num_parents = SIERRA_NUM_CMN_PLLC_PARENTS; 751 init->name = clk_name; 752 753 mux->pfdclk_sel_preg = pfdclk1_sel_field; 754 mux->plllc1en_field = plllc1en_field; 755 mux->termen_field = termen_field; 756 mux->hw.init = init; 757 758 ret = devm_clk_hw_register(dev, &mux->hw); 759 if (ret) 760 return ret; 761 762 sp->clk_data.hws[clk_index] = &mux->hw; 763 764 sp->pll_clks[clk_index] = devm_clk_hw_get_clk(dev, &mux->hw, 765 clk_names[clk_index]); 766 767 return 0; 768 } 769 770 static int cdns_sierra_phy_register_pll_mux(struct cdns_sierra_phy *sp) 771 { 772 struct regmap_field *pfdclk1_sel_field; 773 struct regmap_field *plllc1en_field; 774 struct regmap_field *termen_field; 775 struct device *dev = sp->dev; 776 int ret = 0, i, clk_index; 777 778 clk_index = CDNS_SIERRA_PLL_CMNLC; 779 for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++, clk_index++) { 780 pfdclk1_sel_field = sp->cmn_plllc_pfdclk1_sel_preg[i]; 781 plllc1en_field = sp->cmn_refrcv_refclk_plllc1en_preg[i]; 782 termen_field = sp->cmn_refrcv_refclk_termen_preg[i]; 783 784 ret = cdns_sierra_pll_mux_register(sp, pfdclk1_sel_field, plllc1en_field, 785 termen_field, clk_index); 786 if (ret) { 787 dev_err(dev, "Fail to register cmn plllc mux\n"); 788 return ret; 789 } 790 } 791 792 return 0; 793 } 794 795 static int cdns_sierra_derived_refclk_enable(struct clk_hw *hw) 796 { 797 struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw); 798 799 regmap_field_write(derived_refclk->cmn_plllc_clk1_en_preg, 0x1); 800 801 /* Programming to get 100Mhz clock output in ref_der_clk_out 5GHz VCO/50 = 100MHz */ 802 regmap_field_write(derived_refclk->cmn_plllc_clk1outdiv_preg, 0x2E); 803 804 return 0; 805 } 806 807 static void cdns_sierra_derived_refclk_disable(struct clk_hw *hw) 808 { 809 struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw); 810 811 regmap_field_write(derived_refclk->cmn_plllc_clk1_en_preg, 0); 812 } 813 814 static int cdns_sierra_derived_refclk_is_enabled(struct clk_hw *hw) 815 { 816 struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw); 817 int val; 818 819 regmap_field_read(derived_refclk->cmn_plllc_clk1_en_preg, &val); 820 821 return !!val; 822 } 823 824 static const struct clk_ops cdns_sierra_derived_refclk_ops = { 825 .enable = cdns_sierra_derived_refclk_enable, 826 .disable = cdns_sierra_derived_refclk_disable, 827 .is_enabled = cdns_sierra_derived_refclk_is_enabled, 828 }; 829 830 static int cdns_sierra_derived_refclk_register(struct cdns_sierra_phy *sp) 831 { 832 struct cdns_sierra_derived_refclk *derived_refclk; 833 struct device *dev = sp->dev; 834 struct regmap_field *field; 835 struct clk_init_data *init; 836 struct regmap *regmap; 837 char clk_name[100]; 838 int ret; 839 840 derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL); 841 if (!derived_refclk) 842 return -ENOMEM; 843 844 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 845 clk_names[CDNS_SIERRA_DERIVED_REFCLK]); 846 847 init = &derived_refclk->clk_data; 848 849 init->ops = &cdns_sierra_derived_refclk_ops; 850 init->flags = 0; 851 init->name = clk_name; 852 853 regmap = sp->regmap_common_cdb; 854 855 field = devm_regmap_field_alloc(dev, regmap, cmn_plllc_clk1outdiv_preg); 856 if (IS_ERR(field)) { 857 dev_err(dev, "cmn_plllc_clk1outdiv_preg reg field init failed\n"); 858 return PTR_ERR(field); 859 } 860 derived_refclk->cmn_plllc_clk1outdiv_preg = field; 861 862 field = devm_regmap_field_alloc(dev, regmap, cmn_plllc_clk1_en_preg); 863 if (IS_ERR(field)) { 864 dev_err(dev, "cmn_plllc_clk1_en_preg reg field init failed\n"); 865 return PTR_ERR(field); 866 } 867 derived_refclk->cmn_plllc_clk1_en_preg = field; 868 869 derived_refclk->hw.init = init; 870 871 ret = devm_clk_hw_register(dev, &derived_refclk->hw); 872 if (ret) 873 return ret; 874 875 sp->clk_data.hws[CDNS_SIERRA_DERIVED_REFCLK] = &derived_refclk->hw; 876 877 return 0; 878 } 879 880 static void cdns_sierra_clk_unregister(struct cdns_sierra_phy *sp) 881 { 882 struct device *dev = sp->dev; 883 struct device_node *node = dev->of_node; 884 885 of_clk_del_provider(node); 886 } 887 888 static int cdns_sierra_clk_register(struct cdns_sierra_phy *sp) 889 { 890 struct device *dev = sp->dev; 891 struct device_node *node = dev->of_node; 892 int ret; 893 894 ret = cdns_sierra_phy_register_pll_mux(sp); 895 if (ret) { 896 dev_err(dev, "Failed to pll mux clocks\n"); 897 return ret; 898 } 899 900 ret = cdns_sierra_derived_refclk_register(sp); 901 if (ret) { 902 dev_err(dev, "Failed to register derived refclk\n"); 903 return ret; 904 } 905 906 sp->clk_data.num = CDNS_SIERRA_OUTPUT_CLOCKS; 907 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, 908 &sp->clk_data); 909 if (ret) 910 dev_err(dev, "Failed to add clock provider: %s\n", node->name); 911 912 return ret; 913 } 914 915 static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, 916 struct device_node *child) 917 { 918 u32 phy_type; 919 920 if (of_property_read_u32(child, "reg", &inst->mlane)) 921 return -EINVAL; 922 923 if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes)) 924 return -EINVAL; 925 926 if (of_property_read_u32(child, "cdns,phy-type", &phy_type)) 927 return -EINVAL; 928 929 switch (phy_type) { 930 case PHY_TYPE_PCIE: 931 inst->phy_type = TYPE_PCIE; 932 break; 933 case PHY_TYPE_USB3: 934 inst->phy_type = TYPE_USB; 935 break; 936 case PHY_TYPE_SGMII: 937 inst->phy_type = TYPE_SGMII; 938 break; 939 case PHY_TYPE_QSGMII: 940 inst->phy_type = TYPE_QSGMII; 941 break; 942 default: 943 return -EINVAL; 944 } 945 946 inst->ssc_mode = EXTERNAL_SSC; 947 of_property_read_u32(child, "cdns,ssc-mode", &inst->ssc_mode); 948 949 return 0; 950 } 951 952 static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, 953 u32 block_offset, u8 reg_offset_shift, 954 const struct regmap_config *config) 955 { 956 struct cdns_regmap_cdb_context *ctx; 957 958 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 959 if (!ctx) 960 return ERR_PTR(-ENOMEM); 961 962 ctx->dev = dev; 963 ctx->base = base + block_offset; 964 ctx->reg_offset_shift = reg_offset_shift; 965 966 return devm_regmap_init(dev, NULL, ctx, config); 967 } 968 969 static int cdns_regfield_init(struct cdns_sierra_phy *sp) 970 { 971 struct device *dev = sp->dev; 972 struct regmap_field *field; 973 struct reg_field reg_field; 974 struct regmap *regmap; 975 int i; 976 977 regmap = sp->regmap_common_cdb; 978 field = devm_regmap_field_alloc(dev, regmap, macro_id_type); 979 if (IS_ERR(field)) { 980 dev_err(dev, "MACRO_ID_TYPE reg field init failed\n"); 981 return PTR_ERR(field); 982 } 983 sp->macro_id_type = field; 984 985 for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) { 986 reg_field = cmn_plllc_pfdclk1_sel_preg[i].pfdclk_sel_preg; 987 field = devm_regmap_field_alloc(dev, regmap, reg_field); 988 if (IS_ERR(field)) { 989 dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n", i); 990 return PTR_ERR(field); 991 } 992 sp->cmn_plllc_pfdclk1_sel_preg[i] = field; 993 994 reg_field = cmn_plllc_pfdclk1_sel_preg[i].plllc1en_field; 995 field = devm_regmap_field_alloc(dev, regmap, reg_field); 996 if (IS_ERR(field)) { 997 dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n", i); 998 return PTR_ERR(field); 999 } 1000 sp->cmn_refrcv_refclk_plllc1en_preg[i] = field; 1001 1002 reg_field = cmn_plllc_pfdclk1_sel_preg[i].termen_field; 1003 field = devm_regmap_field_alloc(dev, regmap, reg_field); 1004 if (IS_ERR(field)) { 1005 dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n", i); 1006 return PTR_ERR(field); 1007 } 1008 sp->cmn_refrcv_refclk_termen_preg[i] = field; 1009 } 1010 1011 regmap = sp->regmap_phy_pcs_common_cdb; 1012 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); 1013 if (IS_ERR(field)) { 1014 dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n"); 1015 return PTR_ERR(field); 1016 } 1017 sp->phy_pll_cfg_1 = field; 1018 1019 regmap = sp->regmap_phy_pma_common_cdb; 1020 field = devm_regmap_field_alloc(dev, regmap, pma_cmn_ready); 1021 if (IS_ERR(field)) { 1022 dev_err(dev, "PHY_PMA_CMN_CTRL reg field init failed\n"); 1023 return PTR_ERR(field); 1024 } 1025 sp->pma_cmn_ready = field; 1026 1027 for (i = 0; i < SIERRA_MAX_LANES; i++) { 1028 regmap = sp->regmap_lane_cdb[i]; 1029 field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock); 1030 if (IS_ERR(field)) { 1031 dev_err(dev, "P%d_ENABLE reg field init failed\n", i); 1032 return PTR_ERR(field); 1033 } 1034 sp->pllctrl_lock[i] = field; 1035 } 1036 1037 for (i = 0; i < SIERRA_MAX_LANES; i++) { 1038 regmap = sp->regmap_phy_pcs_lane_cdb[i]; 1039 field = devm_regmap_field_alloc(dev, regmap, phy_iso_link_ctrl_1); 1040 if (IS_ERR(field)) { 1041 dev_err(dev, "PHY_ISO_LINK_CTRL reg field init for lane %d failed\n", i); 1042 return PTR_ERR(field); 1043 } 1044 sp->phy_iso_link_ctrl_1[i] = field; 1045 } 1046 1047 return 0; 1048 } 1049 1050 static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, 1051 void __iomem *base, u8 block_offset_shift, 1052 u8 reg_offset_shift) 1053 { 1054 struct device *dev = sp->dev; 1055 struct regmap *regmap; 1056 u32 block_offset; 1057 int i; 1058 1059 for (i = 0; i < SIERRA_MAX_LANES; i++) { 1060 block_offset = SIERRA_LANE_CDB_OFFSET(i, block_offset_shift, 1061 reg_offset_shift); 1062 regmap = cdns_regmap_init(dev, base, block_offset, 1063 reg_offset_shift, 1064 &cdns_sierra_lane_cdb_config[i]); 1065 if (IS_ERR(regmap)) { 1066 dev_err(dev, "Failed to init lane CDB regmap\n"); 1067 return PTR_ERR(regmap); 1068 } 1069 sp->regmap_lane_cdb[i] = regmap; 1070 } 1071 1072 regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET, 1073 reg_offset_shift, 1074 &cdns_sierra_common_cdb_config); 1075 if (IS_ERR(regmap)) { 1076 dev_err(dev, "Failed to init common CDB regmap\n"); 1077 return PTR_ERR(regmap); 1078 } 1079 sp->regmap_common_cdb = regmap; 1080 1081 block_offset = SIERRA_PHY_PCS_COMMON_OFFSET(block_offset_shift); 1082 regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift, 1083 &cdns_sierra_phy_pcs_cmn_cdb_config); 1084 if (IS_ERR(regmap)) { 1085 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n"); 1086 return PTR_ERR(regmap); 1087 } 1088 sp->regmap_phy_pcs_common_cdb = regmap; 1089 1090 for (i = 0; i < SIERRA_MAX_LANES; i++) { 1091 block_offset = SIERRA_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift, 1092 reg_offset_shift); 1093 regmap = cdns_regmap_init(dev, base, block_offset, 1094 reg_offset_shift, 1095 &cdns_sierra_phy_pcs_lane_cdb_config[i]); 1096 if (IS_ERR(regmap)) { 1097 dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n"); 1098 return PTR_ERR(regmap); 1099 } 1100 sp->regmap_phy_pcs_lane_cdb[i] = regmap; 1101 } 1102 1103 block_offset = SIERRA_PHY_PMA_COMMON_OFFSET(block_offset_shift); 1104 regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift, 1105 &cdns_sierra_phy_pma_cmn_cdb_config); 1106 if (IS_ERR(regmap)) { 1107 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n"); 1108 return PTR_ERR(regmap); 1109 } 1110 sp->regmap_phy_pma_common_cdb = regmap; 1111 1112 for (i = 0; i < SIERRA_MAX_LANES; i++) { 1113 block_offset = SIERRA_PHY_PMA_LANE_CDB_OFFSET(i, block_offset_shift, 1114 reg_offset_shift); 1115 regmap = cdns_regmap_init(dev, base, block_offset, 1116 reg_offset_shift, 1117 &cdns_sierra_phy_pma_lane_cdb_config[i]); 1118 if (IS_ERR(regmap)) { 1119 dev_err(dev, "Failed to init PHY PMA lane CDB regmap\n"); 1120 return PTR_ERR(regmap); 1121 } 1122 sp->regmap_phy_pma_lane_cdb[i] = regmap; 1123 } 1124 1125 return 0; 1126 } 1127 1128 static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, 1129 struct device *dev) 1130 { 1131 struct clk *clk; 1132 int ret; 1133 1134 clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); 1135 if (IS_ERR(clk)) { 1136 dev_err(dev, "cmn_refclk_dig_div clock not found\n"); 1137 ret = PTR_ERR(clk); 1138 return ret; 1139 } 1140 sp->input_clks[CMN_REFCLK_DIG_DIV] = clk; 1141 1142 clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); 1143 if (IS_ERR(clk)) { 1144 dev_err(dev, "cmn_refclk1_dig_div clock not found\n"); 1145 ret = PTR_ERR(clk); 1146 return ret; 1147 } 1148 sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk; 1149 1150 return 0; 1151 } 1152 1153 static int cdns_sierra_phy_clk(struct cdns_sierra_phy *sp) 1154 { 1155 struct device *dev = sp->dev; 1156 struct clk *clk; 1157 int ret; 1158 1159 clk = devm_clk_get_optional(dev, "phy_clk"); 1160 if (IS_ERR(clk)) { 1161 dev_err(dev, "failed to get clock phy_clk\n"); 1162 return PTR_ERR(clk); 1163 } 1164 sp->input_clks[PHY_CLK] = clk; 1165 1166 ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); 1167 if (ret) 1168 return ret; 1169 1170 return 0; 1171 } 1172 1173 static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp) 1174 { 1175 int ret; 1176 1177 ret = clk_prepare_enable(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]); 1178 if (ret) 1179 return ret; 1180 1181 ret = clk_prepare_enable(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC1]); 1182 if (ret) 1183 goto err_pll_cmnlc1; 1184 1185 return 0; 1186 1187 err_pll_cmnlc1: 1188 clk_disable_unprepare(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]); 1189 1190 return ret; 1191 } 1192 1193 static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp) 1194 { 1195 clk_disable_unprepare(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC1]); 1196 clk_disable_unprepare(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]); 1197 if (!sp->already_configured) 1198 clk_disable_unprepare(sp->input_clks[PHY_CLK]); 1199 } 1200 1201 static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, 1202 struct device *dev) 1203 { 1204 struct reset_control *rst; 1205 1206 rst = devm_reset_control_get_exclusive(dev, "sierra_reset"); 1207 if (IS_ERR(rst)) { 1208 dev_err(dev, "failed to get reset\n"); 1209 return PTR_ERR(rst); 1210 } 1211 sp->phy_rst = rst; 1212 1213 rst = devm_reset_control_get_optional_exclusive(dev, "sierra_apb"); 1214 if (IS_ERR(rst)) { 1215 dev_err(dev, "failed to get apb reset\n"); 1216 return PTR_ERR(rst); 1217 } 1218 sp->apb_rst = rst; 1219 1220 return 0; 1221 } 1222 1223 static int cdns_sierra_phy_configure_multilink(struct cdns_sierra_phy *sp) 1224 { 1225 const struct cdns_sierra_data *init_data = sp->init_data; 1226 struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals; 1227 enum cdns_sierra_phy_type phy_t1, phy_t2; 1228 struct cdns_sierra_vals *phy_pma_ln_vals; 1229 const struct cdns_reg_pairs *reg_pairs; 1230 struct cdns_sierra_vals *pcs_cmn_vals; 1231 int i, j, node, mlane, num_lanes, ret; 1232 enum cdns_sierra_ssc_mode ssc; 1233 struct regmap *regmap; 1234 u32 num_regs; 1235 1236 /* Maximum 2 links (subnodes) are supported */ 1237 if (sp->nsubnodes != 2) 1238 return -EINVAL; 1239 1240 clk_set_rate(sp->input_clks[CMN_REFCLK_DIG_DIV], 25000000); 1241 clk_set_rate(sp->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); 1242 1243 /* PHY configured to use both PLL LC and LC1 */ 1244 regmap_field_write(sp->phy_pll_cfg_1, 0x1); 1245 1246 phy_t1 = sp->phys[0].phy_type; 1247 phy_t2 = sp->phys[1].phy_type; 1248 1249 /* 1250 * PHY configuration for multi-link operation is done in two steps. 1251 * e.g. Consider a case for a 4 lane PHY with PCIe using 2 lanes and QSGMII other 2 lanes. 1252 * Sierra PHY has 2 PLLs, viz. PLLLC and PLLLC1. So in this case, PLLLC is used for PCIe 1253 * and PLLLC1 is used for QSGMII. PHY is configured in two steps as described below. 1254 * 1255 * [1] For first step, phy_t1 = TYPE_PCIE and phy_t2 = TYPE_QSGMII 1256 * So the register values are selected as [TYPE_PCIE][TYPE_QSGMII][ssc]. 1257 * This will configure PHY registers associated for PCIe (i.e. first protocol) 1258 * involving PLLLC registers and registers for first 2 lanes of PHY. 1259 * [2] In second step, the variables phy_t1 and phy_t2 are swapped. So now, 1260 * phy_t1 = TYPE_QSGMII and phy_t2 = TYPE_PCIE. And the register values are selected as 1261 * [TYPE_QSGMII][TYPE_PCIE][ssc]. 1262 * This will configure PHY registers associated for QSGMII (i.e. second protocol) 1263 * involving PLLLC1 registers and registers for other 2 lanes of PHY. 1264 * 1265 * This completes the PHY configuration for multilink operation. This approach enables 1266 * dividing the large number of PHY register configurations into protocol specific 1267 * smaller groups. 1268 */ 1269 for (node = 0; node < sp->nsubnodes; node++) { 1270 if (node == 1) { 1271 /* 1272 * If first link with phy_t1 is configured, then configure the PHY for 1273 * second link with phy_t2. Get the array values as [phy_t2][phy_t1][ssc]. 1274 */ 1275 swap(phy_t1, phy_t2); 1276 } 1277 1278 mlane = sp->phys[node].mlane; 1279 ssc = sp->phys[node].ssc_mode; 1280 num_lanes = sp->phys[node].num_lanes; 1281 1282 /* PHY PCS common registers configurations */ 1283 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc]; 1284 if (pcs_cmn_vals) { 1285 reg_pairs = pcs_cmn_vals->reg_pairs; 1286 num_regs = pcs_cmn_vals->num_regs; 1287 regmap = sp->regmap_phy_pcs_common_cdb; 1288 for (i = 0; i < num_regs; i++) 1289 regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); 1290 } 1291 1292 /* PHY PMA lane registers configurations */ 1293 phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_t1][phy_t2][ssc]; 1294 if (phy_pma_ln_vals) { 1295 reg_pairs = phy_pma_ln_vals->reg_pairs; 1296 num_regs = phy_pma_ln_vals->num_regs; 1297 for (i = 0; i < num_lanes; i++) { 1298 regmap = sp->regmap_phy_pma_lane_cdb[i + mlane]; 1299 for (j = 0; j < num_regs; j++) 1300 regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val); 1301 } 1302 } 1303 1304 /* PMA common registers configurations */ 1305 pma_cmn_vals = init_data->pma_cmn_vals[phy_t1][phy_t2][ssc]; 1306 if (pma_cmn_vals) { 1307 reg_pairs = pma_cmn_vals->reg_pairs; 1308 num_regs = pma_cmn_vals->num_regs; 1309 regmap = sp->regmap_common_cdb; 1310 for (i = 0; i < num_regs; i++) 1311 regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); 1312 } 1313 1314 /* PMA lane registers configurations */ 1315 pma_ln_vals = init_data->pma_ln_vals[phy_t1][phy_t2][ssc]; 1316 if (pma_ln_vals) { 1317 reg_pairs = pma_ln_vals->reg_pairs; 1318 num_regs = pma_ln_vals->num_regs; 1319 for (i = 0; i < num_lanes; i++) { 1320 regmap = sp->regmap_lane_cdb[i + mlane]; 1321 for (j = 0; j < num_regs; j++) 1322 regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val); 1323 } 1324 } 1325 1326 if (phy_t1 == TYPE_SGMII || phy_t1 == TYPE_QSGMII) 1327 reset_control_deassert(sp->phys[node].lnk_rst); 1328 } 1329 1330 /* Take the PHY out of reset */ 1331 ret = reset_control_deassert(sp->phy_rst); 1332 if (ret) 1333 return ret; 1334 1335 return 0; 1336 } 1337 1338 static int cdns_sierra_phy_probe(struct platform_device *pdev) 1339 { 1340 struct cdns_sierra_phy *sp; 1341 struct phy_provider *phy_provider; 1342 struct device *dev = &pdev->dev; 1343 const struct cdns_sierra_data *data; 1344 unsigned int id_value; 1345 int ret, node = 0; 1346 void __iomem *base; 1347 struct device_node *dn = dev->of_node, *child; 1348 1349 if (of_get_child_count(dn) == 0) 1350 return -ENODEV; 1351 1352 /* Get init data for this PHY */ 1353 data = of_device_get_match_data(dev); 1354 if (!data) 1355 return -EINVAL; 1356 1357 sp = devm_kzalloc(dev, struct_size(sp, clk_data.hws, 1358 CDNS_SIERRA_OUTPUT_CLOCKS), 1359 GFP_KERNEL); 1360 if (!sp) 1361 return -ENOMEM; 1362 dev_set_drvdata(dev, sp); 1363 sp->dev = dev; 1364 sp->init_data = data; 1365 1366 base = devm_platform_ioremap_resource(pdev, 0); 1367 if (IS_ERR(base)) { 1368 dev_err(dev, "missing \"reg\"\n"); 1369 return PTR_ERR(base); 1370 } 1371 1372 ret = cdns_regmap_init_blocks(sp, base, data->block_offset_shift, 1373 data->reg_offset_shift); 1374 if (ret) 1375 return ret; 1376 1377 ret = cdns_regfield_init(sp); 1378 if (ret) 1379 return ret; 1380 1381 platform_set_drvdata(pdev, sp); 1382 1383 ret = cdns_sierra_phy_get_clocks(sp, dev); 1384 if (ret) 1385 return ret; 1386 1387 ret = cdns_sierra_clk_register(sp); 1388 if (ret) 1389 return ret; 1390 1391 ret = cdns_sierra_phy_enable_clocks(sp); 1392 if (ret) 1393 goto unregister_clk; 1394 1395 regmap_field_read(sp->pma_cmn_ready, &sp->already_configured); 1396 1397 if (!sp->already_configured) { 1398 ret = cdns_sierra_phy_clk(sp); 1399 if (ret) 1400 goto clk_disable; 1401 1402 ret = cdns_sierra_phy_get_resets(sp, dev); 1403 if (ret) 1404 goto clk_disable; 1405 1406 /* Enable APB */ 1407 reset_control_deassert(sp->apb_rst); 1408 } 1409 1410 /* Check that PHY is present */ 1411 regmap_field_read(sp->macro_id_type, &id_value); 1412 if (sp->init_data->id_value != id_value) { 1413 ret = -EINVAL; 1414 goto ctrl_assert; 1415 } 1416 1417 sp->autoconf = of_property_read_bool(dn, "cdns,autoconf"); 1418 1419 for_each_available_child_of_node(dn, child) { 1420 struct phy *gphy; 1421 1422 if (!(of_node_name_eq(child, "phy") || 1423 of_node_name_eq(child, "link"))) 1424 continue; 1425 1426 sp->phys[node].lnk_rst = 1427 of_reset_control_array_get_exclusive(child); 1428 1429 if (IS_ERR(sp->phys[node].lnk_rst)) { 1430 dev_err(dev, "failed to get reset %s\n", 1431 child->full_name); 1432 ret = PTR_ERR(sp->phys[node].lnk_rst); 1433 of_node_put(child); 1434 goto put_control; 1435 } 1436 1437 if (!sp->autoconf) { 1438 ret = cdns_sierra_get_optional(&sp->phys[node], child); 1439 if (ret) { 1440 dev_err(dev, "missing property in node %s\n", 1441 child->name); 1442 of_node_put(child); 1443 reset_control_put(sp->phys[node].lnk_rst); 1444 goto put_control; 1445 } 1446 } 1447 1448 sp->num_lanes += sp->phys[node].num_lanes; 1449 1450 if (!sp->already_configured) 1451 gphy = devm_phy_create(dev, child, &ops); 1452 else 1453 gphy = devm_phy_create(dev, child, &noop_ops); 1454 if (IS_ERR(gphy)) { 1455 ret = PTR_ERR(gphy); 1456 of_node_put(child); 1457 reset_control_put(sp->phys[node].lnk_rst); 1458 goto put_control; 1459 } 1460 sp->phys[node].phy = gphy; 1461 phy_set_drvdata(gphy, &sp->phys[node]); 1462 1463 node++; 1464 } 1465 sp->nsubnodes = node; 1466 1467 if (sp->num_lanes > SIERRA_MAX_LANES) { 1468 ret = -EINVAL; 1469 dev_err(dev, "Invalid lane configuration\n"); 1470 goto put_control; 1471 } 1472 1473 /* If more than one subnode, configure the PHY as multilink */ 1474 if (!sp->already_configured && !sp->autoconf && sp->nsubnodes > 1) { 1475 ret = cdns_sierra_phy_configure_multilink(sp); 1476 if (ret) 1477 goto put_control; 1478 } 1479 1480 pm_runtime_enable(dev); 1481 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1482 if (IS_ERR(phy_provider)) { 1483 ret = PTR_ERR(phy_provider); 1484 goto put_control; 1485 } 1486 1487 return 0; 1488 1489 put_control: 1490 while (--node >= 0) 1491 reset_control_put(sp->phys[node].lnk_rst); 1492 ctrl_assert: 1493 if (!sp->already_configured) 1494 reset_control_assert(sp->apb_rst); 1495 clk_disable: 1496 cdns_sierra_phy_disable_clocks(sp); 1497 unregister_clk: 1498 cdns_sierra_clk_unregister(sp); 1499 return ret; 1500 } 1501 1502 static void cdns_sierra_phy_remove(struct platform_device *pdev) 1503 { 1504 struct cdns_sierra_phy *phy = platform_get_drvdata(pdev); 1505 int i; 1506 1507 reset_control_assert(phy->phy_rst); 1508 reset_control_assert(phy->apb_rst); 1509 pm_runtime_disable(&pdev->dev); 1510 1511 cdns_sierra_phy_disable_clocks(phy); 1512 /* 1513 * The device level resets will be put automatically. 1514 * Need to put the subnode resets here though. 1515 */ 1516 for (i = 0; i < phy->nsubnodes; i++) { 1517 reset_control_assert(phy->phys[i].lnk_rst); 1518 reset_control_put(phy->phys[i].lnk_rst); 1519 } 1520 1521 cdns_sierra_clk_unregister(phy); 1522 } 1523 1524 /* SGMII PHY PMA lane configuration */ 1525 static struct cdns_reg_pairs sgmii_phy_pma_ln_regs[] = { 1526 {0x9010, SIERRA_PHY_PMA_XCVR_CTRL} 1527 }; 1528 1529 static struct cdns_sierra_vals sgmii_phy_pma_ln_vals = { 1530 .reg_pairs = sgmii_phy_pma_ln_regs, 1531 .num_regs = ARRAY_SIZE(sgmii_phy_pma_ln_regs), 1532 }; 1533 1534 /* SGMII refclk 100MHz, no ssc, opt3 and GE1 links using PLL LC1 */ 1535 static const struct cdns_reg_pairs sgmii_100_no_ssc_plllc1_opt3_cmn_regs[] = { 1536 {0x002D, SIERRA_CMN_PLLLC1_FBDIV_INT_PREG}, 1537 {0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG}, 1538 {0x1005, SIERRA_CMN_PLLLC1_CLK0_PREG}, 1539 {0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG}, 1540 {0x0800, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG} 1541 }; 1542 1543 static const struct cdns_reg_pairs sgmii_100_no_ssc_plllc1_opt3_ln_regs[] = { 1544 {0x688E, SIERRA_DET_STANDEC_D_PREG}, 1545 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1546 {0x0FFE, SIERRA_PSC_RX_A0_PREG}, 1547 {0x0106, SIERRA_PLLCTRL_FBDIV_MODE01_PREG}, 1548 {0x0013, SIERRA_PLLCTRL_SUBRATE_PREG}, 1549 {0x0003, SIERRA_PLLCTRL_GEN_A_PREG}, 1550 {0x0106, SIERRA_PLLCTRL_GEN_D_PREG}, 1551 {0x5231, SIERRA_PLLCTRL_CPGAIN_MODE_PREG }, 1552 {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, 1553 {0x9702, SIERRA_DRVCTRL_BOOST_PREG}, 1554 {0x0051, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1555 {0x3C0E, SIERRA_CREQ_CCLKDET_MODE01_PREG}, 1556 {0x3220, SIERRA_CREQ_FSMCLK_SEL_PREG}, 1557 {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, 1558 {0x0002, SIERRA_DEQ_PHALIGN_CTRL}, 1559 {0x0186, SIERRA_DEQ_GLUT0}, 1560 {0x0186, SIERRA_DEQ_GLUT1}, 1561 {0x0186, SIERRA_DEQ_GLUT2}, 1562 {0x0186, SIERRA_DEQ_GLUT3}, 1563 {0x0186, SIERRA_DEQ_GLUT4}, 1564 {0x0861, SIERRA_DEQ_ALUT0}, 1565 {0x07E0, SIERRA_DEQ_ALUT1}, 1566 {0x079E, SIERRA_DEQ_ALUT2}, 1567 {0x071D, SIERRA_DEQ_ALUT3}, 1568 {0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG}, 1569 {0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, 1570 {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1571 {0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG}, 1572 {0x0033, SIERRA_DEQ_PICTRL_PREG}, 1573 {0x0000, SIERRA_CPI_OUTBUF_RATESEL_PREG}, 1574 {0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG}, 1575 {0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1576 {0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG} 1577 }; 1578 1579 static struct cdns_sierra_vals sgmii_100_no_ssc_plllc1_opt3_cmn_vals = { 1580 .reg_pairs = sgmii_100_no_ssc_plllc1_opt3_cmn_regs, 1581 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_plllc1_opt3_cmn_regs), 1582 }; 1583 1584 static struct cdns_sierra_vals sgmii_100_no_ssc_plllc1_opt3_ln_vals = { 1585 .reg_pairs = sgmii_100_no_ssc_plllc1_opt3_ln_regs, 1586 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_plllc1_opt3_ln_regs), 1587 }; 1588 1589 /* QSGMII PHY PMA lane configuration */ 1590 static struct cdns_reg_pairs qsgmii_phy_pma_ln_regs[] = { 1591 {0x9010, SIERRA_PHY_PMA_XCVR_CTRL} 1592 }; 1593 1594 static struct cdns_sierra_vals qsgmii_phy_pma_ln_vals = { 1595 .reg_pairs = qsgmii_phy_pma_ln_regs, 1596 .num_regs = ARRAY_SIZE(qsgmii_phy_pma_ln_regs), 1597 }; 1598 1599 /* QSGMII refclk 100MHz, 20b, opt1, No BW cal, no ssc, PLL LC1 */ 1600 static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_cmn_regs[] = { 1601 {0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG}, 1602 {0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG}, 1603 {0x0000, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG} 1604 }; 1605 1606 static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_ln_regs[] = { 1607 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1608 {0x0252, SIERRA_DET_STANDEC_E_PREG}, 1609 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1610 {0x0FFE, SIERRA_PSC_RX_A0_PREG}, 1611 {0x0011, SIERRA_PLLCTRL_SUBRATE_PREG}, 1612 {0x0001, SIERRA_PLLCTRL_GEN_A_PREG}, 1613 {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, 1614 {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, 1615 {0x0089, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1616 {0x3C3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, 1617 {0x3222, SIERRA_CREQ_FSMCLK_SEL_PREG}, 1618 {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, 1619 {0x8422, SIERRA_CTLELUT_CTRL_PREG}, 1620 {0x4111, SIERRA_DFE_ECMP_RATESEL_PREG}, 1621 {0x4111, SIERRA_DFE_SMP_RATESEL_PREG}, 1622 {0x0002, SIERRA_DEQ_PHALIGN_CTRL}, 1623 {0x9595, SIERRA_DEQ_VGATUNE_CTRL_PREG}, 1624 {0x0186, SIERRA_DEQ_GLUT0}, 1625 {0x0186, SIERRA_DEQ_GLUT1}, 1626 {0x0186, SIERRA_DEQ_GLUT2}, 1627 {0x0186, SIERRA_DEQ_GLUT3}, 1628 {0x0186, SIERRA_DEQ_GLUT4}, 1629 {0x0861, SIERRA_DEQ_ALUT0}, 1630 {0x07E0, SIERRA_DEQ_ALUT1}, 1631 {0x079E, SIERRA_DEQ_ALUT2}, 1632 {0x071D, SIERRA_DEQ_ALUT3}, 1633 {0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG}, 1634 {0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, 1635 {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1636 {0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG}, 1637 {0x0033, SIERRA_DEQ_PICTRL_PREG}, 1638 {0x0660, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, 1639 {0x00D5, SIERRA_CPI_OUTBUF_RATESEL_PREG}, 1640 {0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG}, 1641 {0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1642 {0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG} 1643 }; 1644 1645 static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_cmn_vals = { 1646 .reg_pairs = qsgmii_100_no_ssc_plllc1_cmn_regs, 1647 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_cmn_regs), 1648 }; 1649 1650 static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_ln_vals = { 1651 .reg_pairs = qsgmii_100_no_ssc_plllc1_ln_regs, 1652 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_ln_regs), 1653 }; 1654 1655 /* PCIE PHY PCS common configuration */ 1656 static struct cdns_reg_pairs pcie_phy_pcs_cmn_regs[] = { 1657 {0x0430, SIERRA_PHY_PIPE_CMN_CTRL1} 1658 }; 1659 1660 static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = { 1661 .reg_pairs = pcie_phy_pcs_cmn_regs, 1662 .num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs), 1663 }; 1664 1665 /* refclk100MHz_32b_PCIe_cmn_pll_no_ssc, pcie_links_using_plllc, pipe_bw_3 */ 1666 static const struct cdns_reg_pairs pcie_100_no_ssc_plllc_cmn_regs[] = { 1667 {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 1668 {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 1669 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 1670 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG} 1671 }; 1672 1673 /* 1674 * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc, 1675 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 1676 */ 1677 static const struct cdns_reg_pairs ml_pcie_100_no_ssc_ln_regs[] = { 1678 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1679 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1680 {0x0004, SIERRA_PSC_LN_A3_PREG}, 1681 {0x0004, SIERRA_PSC_LN_A4_PREG}, 1682 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1683 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 1684 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 1685 {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 1686 {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 1687 {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1688 {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1689 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 1690 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 1691 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1692 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1693 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1694 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1695 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1696 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 1697 {0x0041, SIERRA_DEQ_GLUT0}, 1698 {0x0082, SIERRA_DEQ_GLUT1}, 1699 {0x00C3, SIERRA_DEQ_GLUT2}, 1700 {0x0145, SIERRA_DEQ_GLUT3}, 1701 {0x0186, SIERRA_DEQ_GLUT4}, 1702 {0x09E7, SIERRA_DEQ_ALUT0}, 1703 {0x09A6, SIERRA_DEQ_ALUT1}, 1704 {0x0965, SIERRA_DEQ_ALUT2}, 1705 {0x08E3, SIERRA_DEQ_ALUT3}, 1706 {0x00FA, SIERRA_DEQ_DFETAP0}, 1707 {0x00FA, SIERRA_DEQ_DFETAP1}, 1708 {0x00FA, SIERRA_DEQ_DFETAP2}, 1709 {0x00FA, SIERRA_DEQ_DFETAP3}, 1710 {0x00FA, SIERRA_DEQ_DFETAP4}, 1711 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 1712 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 1713 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 1714 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1715 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 1716 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 1717 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 1718 {0x002B, SIERRA_CPI_TRIM_PREG}, 1719 {0x0003, SIERRA_EPI_CTRL_PREG}, 1720 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 1721 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1722 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 1723 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 1724 }; 1725 1726 static struct cdns_sierra_vals pcie_100_no_ssc_plllc_cmn_vals = { 1727 .reg_pairs = pcie_100_no_ssc_plllc_cmn_regs, 1728 .num_regs = ARRAY_SIZE(pcie_100_no_ssc_plllc_cmn_regs), 1729 }; 1730 1731 static struct cdns_sierra_vals ml_pcie_100_no_ssc_ln_vals = { 1732 .reg_pairs = ml_pcie_100_no_ssc_ln_regs, 1733 .num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_ln_regs), 1734 }; 1735 1736 /* 1737 * TI J721E: 1738 * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc, 1739 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 1740 */ 1741 static const struct cdns_reg_pairs ti_ml_pcie_100_no_ssc_ln_regs[] = { 1742 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1743 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1744 {0x0004, SIERRA_PSC_LN_A3_PREG}, 1745 {0x0004, SIERRA_PSC_LN_A4_PREG}, 1746 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1747 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 1748 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 1749 {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 1750 {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 1751 {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1752 {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1753 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 1754 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 1755 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1756 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1757 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1758 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1759 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1760 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 1761 {0x0041, SIERRA_DEQ_GLUT0}, 1762 {0x0082, SIERRA_DEQ_GLUT1}, 1763 {0x00C3, SIERRA_DEQ_GLUT2}, 1764 {0x0145, SIERRA_DEQ_GLUT3}, 1765 {0x0186, SIERRA_DEQ_GLUT4}, 1766 {0x09E7, SIERRA_DEQ_ALUT0}, 1767 {0x09A6, SIERRA_DEQ_ALUT1}, 1768 {0x0965, SIERRA_DEQ_ALUT2}, 1769 {0x08E3, SIERRA_DEQ_ALUT3}, 1770 {0x00FA, SIERRA_DEQ_DFETAP0}, 1771 {0x00FA, SIERRA_DEQ_DFETAP1}, 1772 {0x00FA, SIERRA_DEQ_DFETAP2}, 1773 {0x00FA, SIERRA_DEQ_DFETAP3}, 1774 {0x00FA, SIERRA_DEQ_DFETAP4}, 1775 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 1776 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 1777 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 1778 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1779 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 1780 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 1781 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 1782 {0x002B, SIERRA_CPI_TRIM_PREG}, 1783 {0x0003, SIERRA_EPI_CTRL_PREG}, 1784 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 1785 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1786 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 1787 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}, 1788 {0x0002, SIERRA_TX_RCVDET_OVRD_PREG} 1789 }; 1790 1791 static struct cdns_sierra_vals ti_ml_pcie_100_no_ssc_ln_vals = { 1792 .reg_pairs = ti_ml_pcie_100_no_ssc_ln_regs, 1793 .num_regs = ARRAY_SIZE(ti_ml_pcie_100_no_ssc_ln_regs), 1794 }; 1795 1796 /* refclk100MHz_32b_PCIe_cmn_pll_int_ssc, pcie_links_using_plllc, pipe_bw_3 */ 1797 static const struct cdns_reg_pairs pcie_100_int_ssc_plllc_cmn_regs[] = { 1798 {0x000E, SIERRA_CMN_PLLLC_MODE_PREG}, 1799 {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 1800 {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 1801 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 1802 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 1803 {0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG}, 1804 {0x7F80, SIERRA_CMN_PLLLC_SS_PREG}, 1805 {0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG}, 1806 {0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG}, 1807 {0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}, 1808 {0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG} 1809 }; 1810 1811 /* 1812 * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc, 1813 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 1814 */ 1815 static const struct cdns_reg_pairs ml_pcie_100_int_ssc_ln_regs[] = { 1816 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1817 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1818 {0x0004, SIERRA_PSC_LN_A3_PREG}, 1819 {0x0004, SIERRA_PSC_LN_A4_PREG}, 1820 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1821 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 1822 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 1823 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 1824 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 1825 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 1826 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1827 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1828 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 1829 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 1830 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 1831 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 1832 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1833 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1834 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1835 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1836 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1837 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 1838 {0x0041, SIERRA_DEQ_GLUT0}, 1839 {0x0082, SIERRA_DEQ_GLUT1}, 1840 {0x00C3, SIERRA_DEQ_GLUT2}, 1841 {0x0145, SIERRA_DEQ_GLUT3}, 1842 {0x0186, SIERRA_DEQ_GLUT4}, 1843 {0x09E7, SIERRA_DEQ_ALUT0}, 1844 {0x09A6, SIERRA_DEQ_ALUT1}, 1845 {0x0965, SIERRA_DEQ_ALUT2}, 1846 {0x08E3, SIERRA_DEQ_ALUT3}, 1847 {0x00FA, SIERRA_DEQ_DFETAP0}, 1848 {0x00FA, SIERRA_DEQ_DFETAP1}, 1849 {0x00FA, SIERRA_DEQ_DFETAP2}, 1850 {0x00FA, SIERRA_DEQ_DFETAP3}, 1851 {0x00FA, SIERRA_DEQ_DFETAP4}, 1852 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 1853 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 1854 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 1855 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1856 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 1857 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 1858 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 1859 {0x002B, SIERRA_CPI_TRIM_PREG}, 1860 {0x0003, SIERRA_EPI_CTRL_PREG}, 1861 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 1862 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1863 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 1864 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 1865 }; 1866 1867 static struct cdns_sierra_vals pcie_100_int_ssc_plllc_cmn_vals = { 1868 .reg_pairs = pcie_100_int_ssc_plllc_cmn_regs, 1869 .num_regs = ARRAY_SIZE(pcie_100_int_ssc_plllc_cmn_regs), 1870 }; 1871 1872 static struct cdns_sierra_vals ml_pcie_100_int_ssc_ln_vals = { 1873 .reg_pairs = ml_pcie_100_int_ssc_ln_regs, 1874 .num_regs = ARRAY_SIZE(ml_pcie_100_int_ssc_ln_regs), 1875 }; 1876 1877 /* 1878 * TI J721E: 1879 * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc, 1880 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 1881 */ 1882 static const struct cdns_reg_pairs ti_ml_pcie_100_int_ssc_ln_regs[] = { 1883 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1884 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1885 {0x0004, SIERRA_PSC_LN_A3_PREG}, 1886 {0x0004, SIERRA_PSC_LN_A4_PREG}, 1887 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1888 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 1889 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 1890 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 1891 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 1892 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 1893 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1894 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1895 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 1896 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 1897 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 1898 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 1899 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1900 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1901 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1902 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1903 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1904 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 1905 {0x0041, SIERRA_DEQ_GLUT0}, 1906 {0x0082, SIERRA_DEQ_GLUT1}, 1907 {0x00C3, SIERRA_DEQ_GLUT2}, 1908 {0x0145, SIERRA_DEQ_GLUT3}, 1909 {0x0186, SIERRA_DEQ_GLUT4}, 1910 {0x09E7, SIERRA_DEQ_ALUT0}, 1911 {0x09A6, SIERRA_DEQ_ALUT1}, 1912 {0x0965, SIERRA_DEQ_ALUT2}, 1913 {0x08E3, SIERRA_DEQ_ALUT3}, 1914 {0x00FA, SIERRA_DEQ_DFETAP0}, 1915 {0x00FA, SIERRA_DEQ_DFETAP1}, 1916 {0x00FA, SIERRA_DEQ_DFETAP2}, 1917 {0x00FA, SIERRA_DEQ_DFETAP3}, 1918 {0x00FA, SIERRA_DEQ_DFETAP4}, 1919 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 1920 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 1921 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 1922 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1923 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 1924 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 1925 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 1926 {0x002B, SIERRA_CPI_TRIM_PREG}, 1927 {0x0003, SIERRA_EPI_CTRL_PREG}, 1928 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 1929 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1930 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 1931 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}, 1932 {0x0002, SIERRA_TX_RCVDET_OVRD_PREG} 1933 }; 1934 1935 static struct cdns_sierra_vals ti_ml_pcie_100_int_ssc_ln_vals = { 1936 .reg_pairs = ti_ml_pcie_100_int_ssc_ln_regs, 1937 .num_regs = ARRAY_SIZE(ti_ml_pcie_100_int_ssc_ln_regs), 1938 }; 1939 1940 /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc, pcie_links_using_plllc, pipe_bw_3 */ 1941 static const struct cdns_reg_pairs pcie_100_ext_ssc_plllc_cmn_regs[] = { 1942 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 1943 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 1944 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 1945 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 1946 {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} 1947 }; 1948 1949 /* 1950 * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc, 1951 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 1952 */ 1953 static const struct cdns_reg_pairs ml_pcie_100_ext_ssc_ln_regs[] = { 1954 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1955 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1956 {0x0004, SIERRA_PSC_LN_A3_PREG}, 1957 {0x0004, SIERRA_PSC_LN_A4_PREG}, 1958 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1959 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 1960 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 1961 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 1962 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 1963 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 1964 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1965 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1966 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 1967 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 1968 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 1969 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 1970 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1971 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1972 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1973 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1974 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1975 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 1976 {0x0041, SIERRA_DEQ_GLUT0}, 1977 {0x0082, SIERRA_DEQ_GLUT1}, 1978 {0x00C3, SIERRA_DEQ_GLUT2}, 1979 {0x0145, SIERRA_DEQ_GLUT3}, 1980 {0x0186, SIERRA_DEQ_GLUT4}, 1981 {0x09E7, SIERRA_DEQ_ALUT0}, 1982 {0x09A6, SIERRA_DEQ_ALUT1}, 1983 {0x0965, SIERRA_DEQ_ALUT2}, 1984 {0x08E3, SIERRA_DEQ_ALUT3}, 1985 {0x00FA, SIERRA_DEQ_DFETAP0}, 1986 {0x00FA, SIERRA_DEQ_DFETAP1}, 1987 {0x00FA, SIERRA_DEQ_DFETAP2}, 1988 {0x00FA, SIERRA_DEQ_DFETAP3}, 1989 {0x00FA, SIERRA_DEQ_DFETAP4}, 1990 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 1991 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 1992 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 1993 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1994 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 1995 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 1996 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 1997 {0x002B, SIERRA_CPI_TRIM_PREG}, 1998 {0x0003, SIERRA_EPI_CTRL_PREG}, 1999 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 2000 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 2001 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 2002 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 2003 }; 2004 2005 static struct cdns_sierra_vals pcie_100_ext_ssc_plllc_cmn_vals = { 2006 .reg_pairs = pcie_100_ext_ssc_plllc_cmn_regs, 2007 .num_regs = ARRAY_SIZE(pcie_100_ext_ssc_plllc_cmn_regs), 2008 }; 2009 2010 static struct cdns_sierra_vals ml_pcie_100_ext_ssc_ln_vals = { 2011 .reg_pairs = ml_pcie_100_ext_ssc_ln_regs, 2012 .num_regs = ARRAY_SIZE(ml_pcie_100_ext_ssc_ln_regs), 2013 }; 2014 2015 /* 2016 * TI J721E: 2017 * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc, 2018 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 2019 */ 2020 static const struct cdns_reg_pairs ti_ml_pcie_100_ext_ssc_ln_regs[] = { 2021 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 2022 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 2023 {0x0004, SIERRA_PSC_LN_A3_PREG}, 2024 {0x0004, SIERRA_PSC_LN_A4_PREG}, 2025 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 2026 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 2027 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 2028 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 2029 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 2030 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 2031 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 2032 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 2033 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 2034 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 2035 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 2036 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 2037 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 2038 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 2039 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 2040 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 2041 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 2042 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 2043 {0x0041, SIERRA_DEQ_GLUT0}, 2044 {0x0082, SIERRA_DEQ_GLUT1}, 2045 {0x00C3, SIERRA_DEQ_GLUT2}, 2046 {0x0145, SIERRA_DEQ_GLUT3}, 2047 {0x0186, SIERRA_DEQ_GLUT4}, 2048 {0x09E7, SIERRA_DEQ_ALUT0}, 2049 {0x09A6, SIERRA_DEQ_ALUT1}, 2050 {0x0965, SIERRA_DEQ_ALUT2}, 2051 {0x08E3, SIERRA_DEQ_ALUT3}, 2052 {0x00FA, SIERRA_DEQ_DFETAP0}, 2053 {0x00FA, SIERRA_DEQ_DFETAP1}, 2054 {0x00FA, SIERRA_DEQ_DFETAP2}, 2055 {0x00FA, SIERRA_DEQ_DFETAP3}, 2056 {0x00FA, SIERRA_DEQ_DFETAP4}, 2057 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 2058 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 2059 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 2060 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 2061 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 2062 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 2063 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 2064 {0x002B, SIERRA_CPI_TRIM_PREG}, 2065 {0x0003, SIERRA_EPI_CTRL_PREG}, 2066 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 2067 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 2068 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 2069 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}, 2070 {0x0002, SIERRA_TX_RCVDET_OVRD_PREG} 2071 }; 2072 2073 static struct cdns_sierra_vals ti_ml_pcie_100_ext_ssc_ln_vals = { 2074 .reg_pairs = ti_ml_pcie_100_ext_ssc_ln_regs, 2075 .num_regs = ARRAY_SIZE(ti_ml_pcie_100_ext_ssc_ln_regs), 2076 }; 2077 2078 /* refclk100MHz_32b_PCIe_cmn_pll_no_ssc */ 2079 static const struct cdns_reg_pairs cdns_pcie_cmn_regs_no_ssc[] = { 2080 {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 2081 {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 2082 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 2083 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG} 2084 }; 2085 2086 /* refclk100MHz_32b_PCIe_ln_no_ssc */ 2087 static const struct cdns_reg_pairs cdns_pcie_ln_regs_no_ssc[] = { 2088 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 2089 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 2090 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 2091 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 2092 {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 2093 {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 2094 {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 2095 {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 2096 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 2097 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 2098 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 2099 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 2100 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 2101 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 2102 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 2103 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 2104 {0x0041, SIERRA_DEQ_GLUT0}, 2105 {0x0082, SIERRA_DEQ_GLUT1}, 2106 {0x00C3, SIERRA_DEQ_GLUT2}, 2107 {0x0145, SIERRA_DEQ_GLUT3}, 2108 {0x0186, SIERRA_DEQ_GLUT4}, 2109 {0x09E7, SIERRA_DEQ_ALUT0}, 2110 {0x09A6, SIERRA_DEQ_ALUT1}, 2111 {0x0965, SIERRA_DEQ_ALUT2}, 2112 {0x08E3, SIERRA_DEQ_ALUT3}, 2113 {0x00FA, SIERRA_DEQ_DFETAP0}, 2114 {0x00FA, SIERRA_DEQ_DFETAP1}, 2115 {0x00FA, SIERRA_DEQ_DFETAP2}, 2116 {0x00FA, SIERRA_DEQ_DFETAP3}, 2117 {0x00FA, SIERRA_DEQ_DFETAP4}, 2118 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 2119 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 2120 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 2121 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 2122 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 2123 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 2124 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 2125 {0x002B, SIERRA_CPI_TRIM_PREG}, 2126 {0x0003, SIERRA_EPI_CTRL_PREG}, 2127 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 2128 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 2129 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 2130 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 2131 }; 2132 2133 static struct cdns_sierra_vals pcie_100_no_ssc_cmn_vals = { 2134 .reg_pairs = cdns_pcie_cmn_regs_no_ssc, 2135 .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_no_ssc), 2136 }; 2137 2138 static struct cdns_sierra_vals pcie_100_no_ssc_ln_vals = { 2139 .reg_pairs = cdns_pcie_ln_regs_no_ssc, 2140 .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_no_ssc), 2141 }; 2142 2143 /* refclk100MHz_32b_PCIe_cmn_pll_int_ssc */ 2144 static const struct cdns_reg_pairs cdns_pcie_cmn_regs_int_ssc[] = { 2145 {0x000E, SIERRA_CMN_PLLLC_MODE_PREG}, 2146 {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 2147 {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 2148 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 2149 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 2150 {0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG}, 2151 {0x7F80, SIERRA_CMN_PLLLC_SS_PREG}, 2152 {0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG}, 2153 {0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG}, 2154 {0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}, 2155 {0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG} 2156 }; 2157 2158 /* refclk100MHz_32b_PCIe_ln_int_ssc */ 2159 static const struct cdns_reg_pairs cdns_pcie_ln_regs_int_ssc[] = { 2160 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 2161 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 2162 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 2163 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 2164 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 2165 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 2166 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 2167 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 2168 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 2169 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 2170 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 2171 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 2172 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 2173 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 2174 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 2175 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 2176 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 2177 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 2178 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 2179 {0x0041, SIERRA_DEQ_GLUT0}, 2180 {0x0082, SIERRA_DEQ_GLUT1}, 2181 {0x00C3, SIERRA_DEQ_GLUT2}, 2182 {0x0145, SIERRA_DEQ_GLUT3}, 2183 {0x0186, SIERRA_DEQ_GLUT4}, 2184 {0x09E7, SIERRA_DEQ_ALUT0}, 2185 {0x09A6, SIERRA_DEQ_ALUT1}, 2186 {0x0965, SIERRA_DEQ_ALUT2}, 2187 {0x08E3, SIERRA_DEQ_ALUT3}, 2188 {0x00FA, SIERRA_DEQ_DFETAP0}, 2189 {0x00FA, SIERRA_DEQ_DFETAP1}, 2190 {0x00FA, SIERRA_DEQ_DFETAP2}, 2191 {0x00FA, SIERRA_DEQ_DFETAP3}, 2192 {0x00FA, SIERRA_DEQ_DFETAP4}, 2193 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 2194 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 2195 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 2196 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 2197 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 2198 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 2199 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 2200 {0x002B, SIERRA_CPI_TRIM_PREG}, 2201 {0x0003, SIERRA_EPI_CTRL_PREG}, 2202 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 2203 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 2204 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 2205 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 2206 }; 2207 2208 static struct cdns_sierra_vals pcie_100_int_ssc_cmn_vals = { 2209 .reg_pairs = cdns_pcie_cmn_regs_int_ssc, 2210 .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_int_ssc), 2211 }; 2212 2213 static struct cdns_sierra_vals pcie_100_int_ssc_ln_vals = { 2214 .reg_pairs = cdns_pcie_ln_regs_int_ssc, 2215 .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_int_ssc), 2216 }; 2217 2218 /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */ 2219 static const struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = { 2220 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 2221 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 2222 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 2223 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 2224 {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} 2225 }; 2226 2227 /* refclk100MHz_32b_PCIe_ln_ext_ssc */ 2228 static const struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = { 2229 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 2230 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 2231 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 2232 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 2233 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 2234 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 2235 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 2236 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 2237 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 2238 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 2239 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 2240 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 2241 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 2242 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 2243 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 2244 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 2245 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 2246 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 2247 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 2248 {0x0041, SIERRA_DEQ_GLUT0}, 2249 {0x0082, SIERRA_DEQ_GLUT1}, 2250 {0x00C3, SIERRA_DEQ_GLUT2}, 2251 {0x0145, SIERRA_DEQ_GLUT3}, 2252 {0x0186, SIERRA_DEQ_GLUT4}, 2253 {0x09E7, SIERRA_DEQ_ALUT0}, 2254 {0x09A6, SIERRA_DEQ_ALUT1}, 2255 {0x0965, SIERRA_DEQ_ALUT2}, 2256 {0x08E3, SIERRA_DEQ_ALUT3}, 2257 {0x00FA, SIERRA_DEQ_DFETAP0}, 2258 {0x00FA, SIERRA_DEQ_DFETAP1}, 2259 {0x00FA, SIERRA_DEQ_DFETAP2}, 2260 {0x00FA, SIERRA_DEQ_DFETAP3}, 2261 {0x00FA, SIERRA_DEQ_DFETAP4}, 2262 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 2263 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 2264 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 2265 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 2266 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 2267 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 2268 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 2269 {0x002B, SIERRA_CPI_TRIM_PREG}, 2270 {0x0003, SIERRA_EPI_CTRL_PREG}, 2271 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 2272 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 2273 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 2274 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 2275 }; 2276 2277 static struct cdns_sierra_vals pcie_100_ext_ssc_cmn_vals = { 2278 .reg_pairs = cdns_pcie_cmn_regs_ext_ssc, 2279 .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), 2280 }; 2281 2282 static struct cdns_sierra_vals pcie_100_ext_ssc_ln_vals = { 2283 .reg_pairs = cdns_pcie_ln_regs_ext_ssc, 2284 .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), 2285 }; 2286 2287 /* refclk100MHz_20b_USB_cmn_pll_ext_ssc */ 2288 static const struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = { 2289 {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 2290 {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 2291 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 2292 {0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} 2293 }; 2294 2295 /* refclk100MHz_20b_USB_ln_ext_ssc */ 2296 static const struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = { 2297 {0xFE0A, SIERRA_DET_STANDEC_A_PREG}, 2298 {0x000F, SIERRA_DET_STANDEC_B_PREG}, 2299 {0x55A5, SIERRA_DET_STANDEC_C_PREG}, 2300 {0x69ad, SIERRA_DET_STANDEC_D_PREG}, 2301 {0x0241, SIERRA_DET_STANDEC_E_PREG}, 2302 {0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG}, 2303 {0x0014, SIERRA_PSM_A0IN_TMR_PREG}, 2304 {0xCF00, SIERRA_PSM_DIAG_PREG}, 2305 {0x001F, SIERRA_PSC_TX_A0_PREG}, 2306 {0x0007, SIERRA_PSC_TX_A1_PREG}, 2307 {0x0003, SIERRA_PSC_TX_A2_PREG}, 2308 {0x0003, SIERRA_PSC_TX_A3_PREG}, 2309 {0x0FFF, SIERRA_PSC_RX_A0_PREG}, 2310 {0x0003, SIERRA_PSC_RX_A1_PREG}, 2311 {0x0003, SIERRA_PSC_RX_A2_PREG}, 2312 {0x0001, SIERRA_PSC_RX_A3_PREG}, 2313 {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG}, 2314 {0x0406, SIERRA_PLLCTRL_GEN_D_PREG}, 2315 {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, 2316 {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG}, 2317 {0x2512, SIERRA_DFE_BIASTRIM_PREG}, 2318 {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, 2319 {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG}, 2320 {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 2321 {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 2322 {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, 2323 {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 2324 {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG}, 2325 {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, 2326 {0x0000, SIERRA_CREQ_SPARE_PREG}, 2327 {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 2328 {0x8452, SIERRA_CTLELUT_CTRL_PREG}, 2329 {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG}, 2330 {0x4121, SIERRA_DFE_SMP_RATESEL_PREG}, 2331 {0x0003, SIERRA_DEQ_PHALIGN_CTRL}, 2332 {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG}, 2333 {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 2334 {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 2335 {0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 2336 {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 2337 {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG}, 2338 {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG}, 2339 {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG}, 2340 {0x0014, SIERRA_DEQ_GLUT0}, 2341 {0x0014, SIERRA_DEQ_GLUT1}, 2342 {0x0014, SIERRA_DEQ_GLUT2}, 2343 {0x0014, SIERRA_DEQ_GLUT3}, 2344 {0x0014, SIERRA_DEQ_GLUT4}, 2345 {0x0014, SIERRA_DEQ_GLUT5}, 2346 {0x0014, SIERRA_DEQ_GLUT6}, 2347 {0x0014, SIERRA_DEQ_GLUT7}, 2348 {0x0014, SIERRA_DEQ_GLUT8}, 2349 {0x0014, SIERRA_DEQ_GLUT9}, 2350 {0x0014, SIERRA_DEQ_GLUT10}, 2351 {0x0014, SIERRA_DEQ_GLUT11}, 2352 {0x0014, SIERRA_DEQ_GLUT12}, 2353 {0x0014, SIERRA_DEQ_GLUT13}, 2354 {0x0014, SIERRA_DEQ_GLUT14}, 2355 {0x0014, SIERRA_DEQ_GLUT15}, 2356 {0x0014, SIERRA_DEQ_GLUT16}, 2357 {0x0BAE, SIERRA_DEQ_ALUT0}, 2358 {0x0AEB, SIERRA_DEQ_ALUT1}, 2359 {0x0A28, SIERRA_DEQ_ALUT2}, 2360 {0x0965, SIERRA_DEQ_ALUT3}, 2361 {0x08A2, SIERRA_DEQ_ALUT4}, 2362 {0x07DF, SIERRA_DEQ_ALUT5}, 2363 {0x071C, SIERRA_DEQ_ALUT6}, 2364 {0x0659, SIERRA_DEQ_ALUT7}, 2365 {0x0596, SIERRA_DEQ_ALUT8}, 2366 {0x0514, SIERRA_DEQ_ALUT9}, 2367 {0x0492, SIERRA_DEQ_ALUT10}, 2368 {0x0410, SIERRA_DEQ_ALUT11}, 2369 {0x038E, SIERRA_DEQ_ALUT12}, 2370 {0x030C, SIERRA_DEQ_ALUT13}, 2371 {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG}, 2372 {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG}, 2373 {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, 2374 {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 2375 {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG}, 2376 {0x0033, SIERRA_DEQ_PICTRL_PREG}, 2377 {0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG}, 2378 {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, 2379 {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG}, 2380 {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG}, 2381 {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG}, 2382 {0x0005, SIERRA_LFPSDET_SUPPORT_PREG}, 2383 {0x000F, SIERRA_LFPSFILT_NS_PREG}, 2384 {0x0009, SIERRA_LFPSFILT_RD_PREG}, 2385 {0x0001, SIERRA_LFPSFILT_MP_PREG}, 2386 {0x6013, SIERRA_SIGDET_SUPPORT_PREG}, 2387 {0x8013, SIERRA_SDFILT_H2L_A_PREG}, 2388 {0x8009, SIERRA_SDFILT_L2H_PREG}, 2389 {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG}, 2390 {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 2391 {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG} 2392 }; 2393 2394 static struct cdns_sierra_vals usb_100_ext_ssc_cmn_vals = { 2395 .reg_pairs = cdns_usb_cmn_regs_ext_ssc, 2396 .num_regs = ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), 2397 }; 2398 2399 static struct cdns_sierra_vals usb_100_ext_ssc_ln_vals = { 2400 .reg_pairs = cdns_usb_ln_regs_ext_ssc, 2401 .num_regs = ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), 2402 }; 2403 2404 static const struct cdns_sierra_data cdns_map_sierra = { 2405 .id_value = SIERRA_MACRO_ID, 2406 .block_offset_shift = 0x2, 2407 .reg_offset_shift = 0x2, 2408 .pcs_cmn_vals = { 2409 [TYPE_PCIE] = { 2410 [TYPE_NONE] = { 2411 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 2412 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2413 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2414 }, 2415 [TYPE_SGMII] = { 2416 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 2417 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2418 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2419 }, 2420 [TYPE_QSGMII] = { 2421 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 2422 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2423 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2424 }, 2425 }, 2426 }, 2427 .pma_cmn_vals = { 2428 [TYPE_PCIE] = { 2429 [TYPE_NONE] = { 2430 [NO_SSC] = &pcie_100_no_ssc_cmn_vals, 2431 [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals, 2432 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, 2433 }, 2434 [TYPE_SGMII] = { 2435 [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, 2436 [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, 2437 [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, 2438 }, 2439 [TYPE_QSGMII] = { 2440 [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, 2441 [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, 2442 [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, 2443 }, 2444 }, 2445 [TYPE_USB] = { 2446 [TYPE_NONE] = { 2447 [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals, 2448 }, 2449 }, 2450 [TYPE_SGMII] = { 2451 [TYPE_PCIE] = { 2452 [NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, 2453 [EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, 2454 [INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, 2455 }, 2456 }, 2457 [TYPE_QSGMII] = { 2458 [TYPE_PCIE] = { 2459 [NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 2460 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 2461 [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 2462 }, 2463 }, 2464 }, 2465 .pma_ln_vals = { 2466 [TYPE_PCIE] = { 2467 [TYPE_NONE] = { 2468 [NO_SSC] = &pcie_100_no_ssc_ln_vals, 2469 [EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals, 2470 [INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals, 2471 }, 2472 [TYPE_SGMII] = { 2473 [NO_SSC] = &ml_pcie_100_no_ssc_ln_vals, 2474 [EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals, 2475 [INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals, 2476 }, 2477 [TYPE_QSGMII] = { 2478 [NO_SSC] = &ml_pcie_100_no_ssc_ln_vals, 2479 [EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals, 2480 [INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals, 2481 }, 2482 }, 2483 [TYPE_USB] = { 2484 [TYPE_NONE] = { 2485 [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals, 2486 }, 2487 }, 2488 [TYPE_SGMII] = { 2489 [TYPE_PCIE] = { 2490 [NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals, 2491 [EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals, 2492 [INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals, 2493 }, 2494 }, 2495 [TYPE_QSGMII] = { 2496 [TYPE_PCIE] = { 2497 [NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 2498 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 2499 [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 2500 }, 2501 }, 2502 }, 2503 }; 2504 2505 static const struct cdns_sierra_data cdns_ti_map_sierra = { 2506 .id_value = SIERRA_MACRO_ID, 2507 .block_offset_shift = 0x0, 2508 .reg_offset_shift = 0x1, 2509 .pcs_cmn_vals = { 2510 [TYPE_PCIE] = { 2511 [TYPE_NONE] = { 2512 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 2513 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2514 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2515 }, 2516 [TYPE_SGMII] = { 2517 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 2518 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2519 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2520 }, 2521 [TYPE_QSGMII] = { 2522 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 2523 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2524 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2525 }, 2526 }, 2527 }, 2528 .phy_pma_ln_vals = { 2529 [TYPE_SGMII] = { 2530 [TYPE_PCIE] = { 2531 [NO_SSC] = &sgmii_phy_pma_ln_vals, 2532 [EXTERNAL_SSC] = &sgmii_phy_pma_ln_vals, 2533 [INTERNAL_SSC] = &sgmii_phy_pma_ln_vals, 2534 }, 2535 }, 2536 [TYPE_QSGMII] = { 2537 [TYPE_PCIE] = { 2538 [NO_SSC] = &qsgmii_phy_pma_ln_vals, 2539 [EXTERNAL_SSC] = &qsgmii_phy_pma_ln_vals, 2540 [INTERNAL_SSC] = &qsgmii_phy_pma_ln_vals, 2541 }, 2542 }, 2543 }, 2544 .pma_cmn_vals = { 2545 [TYPE_PCIE] = { 2546 [TYPE_NONE] = { 2547 [NO_SSC] = &pcie_100_no_ssc_cmn_vals, 2548 [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals, 2549 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, 2550 }, 2551 [TYPE_SGMII] = { 2552 [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, 2553 [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, 2554 [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, 2555 }, 2556 [TYPE_QSGMII] = { 2557 [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, 2558 [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, 2559 [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, 2560 }, 2561 }, 2562 [TYPE_USB] = { 2563 [TYPE_NONE] = { 2564 [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals, 2565 }, 2566 }, 2567 [TYPE_SGMII] = { 2568 [TYPE_PCIE] = { 2569 [NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, 2570 [EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, 2571 [INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, 2572 }, 2573 }, 2574 [TYPE_QSGMII] = { 2575 [TYPE_PCIE] = { 2576 [NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 2577 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 2578 [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 2579 }, 2580 }, 2581 }, 2582 .pma_ln_vals = { 2583 [TYPE_PCIE] = { 2584 [TYPE_NONE] = { 2585 [NO_SSC] = &pcie_100_no_ssc_ln_vals, 2586 [EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals, 2587 [INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals, 2588 }, 2589 [TYPE_SGMII] = { 2590 [NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals, 2591 [EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals, 2592 [INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals, 2593 }, 2594 [TYPE_QSGMII] = { 2595 [NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals, 2596 [EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals, 2597 [INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals, 2598 }, 2599 }, 2600 [TYPE_USB] = { 2601 [TYPE_NONE] = { 2602 [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals, 2603 }, 2604 }, 2605 [TYPE_SGMII] = { 2606 [TYPE_PCIE] = { 2607 [NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals, 2608 [EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals, 2609 [INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals, 2610 }, 2611 }, 2612 [TYPE_QSGMII] = { 2613 [TYPE_PCIE] = { 2614 [NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 2615 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 2616 [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 2617 }, 2618 }, 2619 }, 2620 }; 2621 2622 static const struct of_device_id cdns_sierra_id_table[] = { 2623 { 2624 .compatible = "cdns,sierra-phy-t0", 2625 .data = &cdns_map_sierra, 2626 }, 2627 { 2628 .compatible = "ti,sierra-phy-t0", 2629 .data = &cdns_ti_map_sierra, 2630 }, 2631 {} 2632 }; 2633 MODULE_DEVICE_TABLE(of, cdns_sierra_id_table); 2634 2635 static struct platform_driver cdns_sierra_driver = { 2636 .probe = cdns_sierra_phy_probe, 2637 .remove_new = cdns_sierra_phy_remove, 2638 .driver = { 2639 .name = "cdns-sierra-phy", 2640 .of_match_table = cdns_sierra_id_table, 2641 }, 2642 }; 2643 module_platform_driver(cdns_sierra_driver); 2644 2645 MODULE_ALIAS("platform:cdns_sierra"); 2646 MODULE_AUTHOR("Cadence Design Systems"); 2647 MODULE_DESCRIPTION("CDNS sierra phy driver"); 2648 MODULE_LICENSE("GPL v2"); 2649