| 48ad55cd | 10-Jul-2026 |
Prathima <Prathima.Lk@amd.com> |
misc: amd-sbi: Add SBTSI ioctl register transfer interface
Implement IOCTL interface for SB-TSI driver to enable userspace access to TSI register read/write operations through the AMD Advanced Platf
misc: amd-sbi: Add SBTSI ioctl register transfer interface
Implement IOCTL interface for SB-TSI driver to enable userspace access to TSI register read/write operations through the AMD Advanced Platform Management Link (APML) protocol. Add an ioctl command (SBTSI_IOCTL_REG_XFER_CMD) that accepts a register address, data byte, and direction flag. The mutex is taken on the ioctl path here; the hwmon path is placed under the same lock in the next patch, which completes serialization between the hwmon and ioctl paths.
Reviewed-by: Akshay Gupta <Akshay.Gupta@amd.com> Signed-off-by: Prathima <Prathima.Lk@amd.com> Link: https://patch.msgid.link/20260710111642.850022-7-Akshay.Gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| f61a6fd4 | 10-Jul-2026 |
Prathima <Prathima.Lk@amd.com> |
misc: amd-sbi: Add support for SB-TSI over I3C
AMD SB-TSI temperature sensors can be accessed over both I2C and I3C buses depending on the platform configuration. Extend the SB-TSI driver to support
misc: amd-sbi: Add support for SB-TSI over I3C
AMD SB-TSI temperature sensors can be accessed over both I2C and I3C buses depending on the platform configuration. Extend the SB-TSI driver to support both I2C and I3C bus interfaces by selecting the appropriate transport based on the probed bus type. The driver maintains backward compatibility with existing I2C deployments while enabling support for systems using the I3C bus. Register both I2C and I3C drivers using module_i3c_i2c_driver() and update the Kconfig dependency from I2C to I3C_OR_I2C.
Reviewed-by: Akshay Gupta <Akshay.Gupta@amd.com> Signed-off-by: Prathima <Prathima.Lk@amd.com> Link: https://patch.msgid.link/20260710111642.850022-6-Akshay.Gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| ba27ea7a | 10-Jul-2026 |
Prathima <Prathima.Lk@amd.com> |
misc: amd-sbi: Consolidate Common SBTSI Probe Path
Refactor shared probe procedures into sbtsi_probe_common() to ensure that I2C and I3C probes focus solely on bus-specific allocation and device con
misc: amd-sbi: Consolidate Common SBTSI Probe Path
Refactor shared probe procedures into sbtsi_probe_common() to ensure that I2C and I3C probes focus solely on bus-specific allocation and device configuration. The utility function reads the configuration register via sbtsi_xfer(), initializes ext_range_mode and read_order, assigns the driver data, and registers the hwmon auxiliary device. Routing register access through sbtsi_xfer() keeps the probe path bus-agnostic, so no transfer logic has to be duplicated when SB-TSI over I3C support is added in a later patch.
Reviewed-by: Akshay Gupta <Akshay.Gupta@amd.com> Signed-off-by: Prathima <Prathima.Lk@amd.com> Link: https://patch.msgid.link/20260710111642.850022-5-Akshay.Gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| d4f8babf | 10-Jul-2026 |
Prathima <Prathima.Lk@amd.com> |
hwmon/misc: amd-sbi: Move sbtsi register transfer to core abstraction
Move the I2C read/write byte operations from the sbtsi hwmon driver into a common sbtsi_xfer() function in tsi-core.c. This deco
hwmon/misc: amd-sbi: Move sbtsi register transfer to core abstraction
Move the I2C read/write byte operations from the sbtsi hwmon driver into a common sbtsi_xfer() function in tsi-core.c. This decouples the hwmon sensor driver from the underlying bus transport, preparing for I3C support in a subsequent patch. This patch does not introduce any functional changes. The updates are limited to code organization/cleanup and should not affect the runtime behavior of the driver
Reviewed-by: Akshay Gupta <Akshay.Gupta@amd.com> Signed-off-by: Prathima <Prathima.Lk@amd.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Link: https://patch.msgid.link/20260710111642.850022-4-Akshay.Gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| 319138ff | 10-Jul-2026 |
Prathima <Prathima.Lk@amd.com> |
hwmon/misc: amd-sbi: Move core sbtsi support from hwmon to misc
Move SBTSI(Side-Band Temperature Sensor Interface) core functionality out of the hwmon-only path and into drivers/misc/amd-sbi so it c
hwmon/misc: amd-sbi: Move core sbtsi support from hwmon to misc
Move SBTSI(Side-Band Temperature Sensor Interface) core functionality out of the hwmon-only path and into drivers/misc/amd-sbi so it can be reused by non-hwmon consumers.
I2C probe parsing is moved from drivers/hwmon/sbtsi_temp.c into drivers/misc/amd-sbi/tsi.c under CONFIG_AMD_SBTSI. The core driver stores struct sbtsi_data on the bus device and registers an auxiliary device amd-sbtsi.temp-sensor.<addr> per target. The current hwmon temp sensor will now require the CONFIG_AMD_SBTSI configuration as a new dependency.
This split prepares the driver for additional interfaces while keeping hwmon support in hwmon subsystem on top of common SBTSI core logic.
Add platform dependencies to clarify this driver is intended to run on the BMC and not on the managed node.
Reviewed-by: Akshay Gupta <Akshay.Gupta@amd.com> Signed-off-by: Prathima <Prathima.Lk@amd.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Link: https://patch.msgid.link/20260710111642.850022-2-Akshay.Gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| eef2a8dd | 18-Mar-2026 |
Akshay Gupta <Akshay.Gupta@amd.com> |
misc: amd-sbi: Add device tree mapping for AMD SBRMI devices
Add device tree mapping to enable SBRMI device support across different models and steppings on the AMD Venice platform.
Reviewed-by: Na
misc: amd-sbi: Add device tree mapping for AMD SBRMI devices
Add device tree mapping to enable SBRMI device support across different models and steppings on the AMD Venice platform.
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <Akshay.Gupta@amd.com> Link: https://patch.msgid.link/20260318112711.2757467-3-Akshay.Gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| 82e12887 | 18-Mar-2026 |
Akshay Gupta <Akshay.Gupta@amd.com> |
misc: amd-sbi: Add check to probe only SBRMI devices
AMD OOB devices are differentiated by their Instance ID, with SBRMI assigned Instance ID 1. Since the device ID match does not consider the Insta
misc: amd-sbi: Add check to probe only SBRMI devices
AMD OOB devices are differentiated by their Instance ID, with SBRMI assigned Instance ID 1. Since the device ID match does not consider the Instance ID, add an explicit check to restrict probing to only the SBRMI device and exclude other OOB devices.
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <Akshay.Gupta@amd.com> Link: https://patch.msgid.link/20260318112711.2757467-2-Akshay.Gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| b5e7fb39 | 18-Mar-2026 |
Akshay Gupta <Akshay.Gupta@amd.com> |
misc: amd-sbi: Add revision support for AMD Venice platform
The AMD Venice platform uses revision 0x31 and a two-byte register address size. Add the revision to the CPUID and MCAMSR protocol functio
misc: amd-sbi: Add revision support for AMD Venice platform
The AMD Venice platform uses revision 0x31 and a two-byte register address size. Add the revision to the CPUID and MCAMSR protocol functions to ensure correct protocol identification.
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <Akshay.Gupta@amd.com> Link: https://patch.msgid.link/20260318112711.2757467-1-Akshay.Gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| 18e4a029 | 15-Sep-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Extend support for MCAMSR protocol for rev 0x21
- MCAMSR protocol for revision 0x21 is updated to include the extended thread supported by the platform. - This modifies the existing
misc: amd-sbi: Extend support for MCAMSR protocol for rev 0x21
- MCAMSR protocol for revision 0x21 is updated to include the extended thread supported by the platform. - This modifies the existing protocol to include additional byte to provide high thread number. - New input structure is defined to address this, as the hardware protocol is tightly coupled with the input structure length
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://patch.msgid.link/20250915103649.1705078-6-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| 87816eb4 | 15-Sep-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Extend support for CPUID protocol for rev 0x21
- CPUID protocol for revision 0x21 is updated to include the extended thread supported by the platform. - This modifies the existing p
misc: amd-sbi: Extend support for CPUID protocol for rev 0x21
- CPUID protocol for revision 0x21 is updated to include the extended thread supported by the platform. - This modifies the existing protocol to include additional byte to provide high thread number. - New input structure is defined to address this, as the hardware protocol is tightly coupled with the input structure length
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://patch.msgid.link/20250915103649.1705078-5-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| dd68c063 | 15-Sep-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: CPUID/MCAMSR protocol for Revision 0x21
- CPUID and MCAMSR protocol for newer platform with revision 0x21 and later is modified as per two byte register address size. - Modify the C
misc: amd-sbi: CPUID/MCAMSR protocol for Revision 0x21
- CPUID and MCAMSR protocol for newer platform with revision 0x21 and later is modified as per two byte register address size. - Modify the CPUID and MCAMSR protocol to return error, "-EOPNOTSUPP", for revision 0x21. - Next set of patches will add support for CPUID and MCAMSR for Turin and later platforms.
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://patch.msgid.link/20250915103649.1705078-4-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| 45392fd4 | 15-Sep-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Add support for Turin platform
- RMI registers addresses in AMD new platforms are 2 bytes, on previous processors the address size is 1 byte. - Implement logic to identify register
misc: amd-sbi: Add support for Turin platform
- RMI registers addresses in AMD new platforms are 2 bytes, on previous processors the address size is 1 byte. - Implement logic to identify register address size at runtime. - The identification is done in first transaction using the Revision register. - The revision register can be read using 1 byte in both, older and newer platforms. - However, sending 1 byte on later platform can cause unrecoverable error.
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://patch.msgid.link/20250915103649.1705078-3-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| 5c7dddd7 | 15-Sep-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Add support for SB-RMI over I3C
AMD EPYC platforms with zen5 and later support APML(SB-RMI) connection to the BMC over I3C bus for faster data transfer up to 12.5 Mhz. I2C and I3C is
misc: amd-sbi: Add support for SB-RMI over I3C
AMD EPYC platforms with zen5 and later support APML(SB-RMI) connection to the BMC over I3C bus for faster data transfer up to 12.5 Mhz. I2C and I3C is supported in same file using module_i3c_i2c_driver() with probe based on dts entry. AMD APML I3C devices support static address for backward compatibility to I2C. I3C static address can be used to assign I3C device dynamic address.
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://patch.msgid.link/20250915103649.1705078-2-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| 16ad3ee5 | 16-Jul-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Explicitly clear in/out arg "mb_in_out"
- New AMD processor will support different input/output for same command. - In some scenarios the input value is not cleared, which will be add
misc: amd-sbi: Explicitly clear in/out arg "mb_in_out"
- New AMD processor will support different input/output for same command. - In some scenarios the input value is not cleared, which will be added to output before reporting the data. - Clearing input explicitly will be a cleaner and safer approach.
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://lore.kernel.org/r/20250716110729.2193725-3-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| bbb40139 | 16-Jul-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Address copy_to/from_user() warning reported in smatch
Smatch warnings are reported for below commit,
Commit bb13a84ed6b7 ("misc: amd-sbi: Add support for CPUID protocol") from Apr 2
misc: amd-sbi: Address copy_to/from_user() warning reported in smatch
Smatch warnings are reported for below commit,
Commit bb13a84ed6b7 ("misc: amd-sbi: Add support for CPUID protocol") from Apr 28, 2025 (linux-next), leads to the following Smatch static checker warning:
drivers/misc/amd-sbi/rmi-core.c:376 apml_rmi_reg_xfer() warn: maybe return -EFAULT instead of the bytes remaining? drivers/misc/amd-sbi/rmi-core.c:394 apml_mailbox_xfer() warn: maybe return -EFAULT instead of the bytes remaining? drivers/misc/amd-sbi/rmi-core.c:411 apml_cpuid_xfer() warn: maybe return -EFAULT instead of the bytes remaining? drivers/misc/amd-sbi/rmi-core.c:428 apml_mcamsr_xfer() warn: maybe return -EFAULT instead of the bytes remaining?
copy_to/from_user() returns number of bytes, not copied. In case data not copied, return "-EFAULT". Additionally, fixes the "-EPROTOTYPE" error return as intended.
Fixes: 35ac2034db72 ("misc: amd-sbi: Add support for AMD_SBI IOCTL") Fixes: bb13a84ed6b7 ("misc: amd-sbi: Add support for CPUID protocol") Fixes: 69b1ba83d21c ("misc: amd-sbi: Add support for read MCA register protocol") Fixes: cf141287b774 ("misc: amd-sbi: Add support for register xfer") Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/all/aDVyO8ByVsceybk9@stanley.mountain/ Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://lore.kernel.org/r/20250716110729.2193725-2-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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