| 18e4a029 | 15-Sep-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Extend support for MCAMSR protocol for rev 0x21
- MCAMSR protocol for revision 0x21 is updated to include the extended thread supported by the platform. - This modifies the existing
misc: amd-sbi: Extend support for MCAMSR protocol for rev 0x21
- MCAMSR protocol for revision 0x21 is updated to include the extended thread supported by the platform. - This modifies the existing protocol to include additional byte to provide high thread number. - New input structure is defined to address this, as the hardware protocol is tightly coupled with the input structure length
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://patch.msgid.link/20250915103649.1705078-6-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| 87816eb4 | 15-Sep-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Extend support for CPUID protocol for rev 0x21
- CPUID protocol for revision 0x21 is updated to include the extended thread supported by the platform. - This modifies the existing p
misc: amd-sbi: Extend support for CPUID protocol for rev 0x21
- CPUID protocol for revision 0x21 is updated to include the extended thread supported by the platform. - This modifies the existing protocol to include additional byte to provide high thread number. - New input structure is defined to address this, as the hardware protocol is tightly coupled with the input structure length
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://patch.msgid.link/20250915103649.1705078-5-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| dd68c063 | 15-Sep-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: CPUID/MCAMSR protocol for Revision 0x21
- CPUID and MCAMSR protocol for newer platform with revision 0x21 and later is modified as per two byte register address size. - Modify the C
misc: amd-sbi: CPUID/MCAMSR protocol for Revision 0x21
- CPUID and MCAMSR protocol for newer platform with revision 0x21 and later is modified as per two byte register address size. - Modify the CPUID and MCAMSR protocol to return error, "-EOPNOTSUPP", for revision 0x21. - Next set of patches will add support for CPUID and MCAMSR for Turin and later platforms.
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://patch.msgid.link/20250915103649.1705078-4-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| 45392fd4 | 15-Sep-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Add support for Turin platform
- RMI registers addresses in AMD new platforms are 2 bytes, on previous processors the address size is 1 byte. - Implement logic to identify register
misc: amd-sbi: Add support for Turin platform
- RMI registers addresses in AMD new platforms are 2 bytes, on previous processors the address size is 1 byte. - Implement logic to identify register address size at runtime. - The identification is done in first transaction using the Revision register. - The revision register can be read using 1 byte in both, older and newer platforms. - However, sending 1 byte on later platform can cause unrecoverable error.
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://patch.msgid.link/20250915103649.1705078-3-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| 5c7dddd7 | 15-Sep-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Add support for SB-RMI over I3C
AMD EPYC platforms with zen5 and later support APML(SB-RMI) connection to the BMC over I3C bus for faster data transfer up to 12.5 Mhz. I2C and I3C is
misc: amd-sbi: Add support for SB-RMI over I3C
AMD EPYC platforms with zen5 and later support APML(SB-RMI) connection to the BMC over I3C bus for faster data transfer up to 12.5 Mhz. I2C and I3C is supported in same file using module_i3c_i2c_driver() with probe based on dts entry. AMD APML I3C devices support static address for backward compatibility to I2C. I3C static address can be used to assign I3C device dynamic address.
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://patch.msgid.link/20250915103649.1705078-2-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| 16ad3ee5 | 16-Jul-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Explicitly clear in/out arg "mb_in_out"
- New AMD processor will support different input/output for same command. - In some scenarios the input value is not cleared, which will be add
misc: amd-sbi: Explicitly clear in/out arg "mb_in_out"
- New AMD processor will support different input/output for same command. - In some scenarios the input value is not cleared, which will be added to output before reporting the data. - Clearing input explicitly will be a cleaner and safer approach.
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://lore.kernel.org/r/20250716110729.2193725-3-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| bbb40139 | 16-Jul-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Address copy_to/from_user() warning reported in smatch
Smatch warnings are reported for below commit,
Commit bb13a84ed6b7 ("misc: amd-sbi: Add support for CPUID protocol") from Apr 2
misc: amd-sbi: Address copy_to/from_user() warning reported in smatch
Smatch warnings are reported for below commit,
Commit bb13a84ed6b7 ("misc: amd-sbi: Add support for CPUID protocol") from Apr 28, 2025 (linux-next), leads to the following Smatch static checker warning:
drivers/misc/amd-sbi/rmi-core.c:376 apml_rmi_reg_xfer() warn: maybe return -EFAULT instead of the bytes remaining? drivers/misc/amd-sbi/rmi-core.c:394 apml_mailbox_xfer() warn: maybe return -EFAULT instead of the bytes remaining? drivers/misc/amd-sbi/rmi-core.c:411 apml_cpuid_xfer() warn: maybe return -EFAULT instead of the bytes remaining? drivers/misc/amd-sbi/rmi-core.c:428 apml_mcamsr_xfer() warn: maybe return -EFAULT instead of the bytes remaining?
copy_to/from_user() returns number of bytes, not copied. In case data not copied, return "-EFAULT". Additionally, fixes the "-EPROTOTYPE" error return as intended.
Fixes: 35ac2034db72 ("misc: amd-sbi: Add support for AMD_SBI IOCTL") Fixes: bb13a84ed6b7 ("misc: amd-sbi: Add support for CPUID protocol") Fixes: 69b1ba83d21c ("misc: amd-sbi: Add support for read MCA register protocol") Fixes: cf141287b774 ("misc: amd-sbi: Add support for register xfer") Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/all/aDVyO8ByVsceybk9@stanley.mountain/ Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://lore.kernel.org/r/20250716110729.2193725-2-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| cf141287 | 28-Apr-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Add support for register xfer
- Provide user register access over IOCTL. Both register read and write are supported. - APML interface does not provide a synchronization method. By d
misc: amd-sbi: Add support for register xfer
- Provide user register access over IOCTL. Both register read and write are supported. - APML interface does not provide a synchronization method. By defining, a register access path, we use APML modules and library for all APML transactions. Without having to use external tools such as i2c-tools, which may cause race conditions.
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://lore.kernel.org/r/20250428063034.2145566-10-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| 69b1ba83 | 28-Apr-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Add support for read MCA register protocol
- AMD provides custom protocol to read Machine Check Architecture(MCA) registers over sideband. The information is accessed for range of
misc: amd-sbi: Add support for read MCA register protocol
- AMD provides custom protocol to read Machine Check Architecture(MCA) registers over sideband. The information is accessed for range of MCA registers by passing register address and thread ID to the protocol. MCA register read command using the register address to access Core::X86::Msr::MCG_CAP which determines the number of MCA banks. Access is read-only
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://lore.kernel.org/r/20250428063034.2145566-9-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| bb13a84e | 28-Apr-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Add support for CPUID protocol
- AMD provides custom protocol to read Processor feature capabilities and configuration information through side band. The information is accessed b
misc: amd-sbi: Add support for CPUID protocol
- AMD provides custom protocol to read Processor feature capabilities and configuration information through side band. The information is accessed by providing CPUID Function, extended function and thread ID to the protocol. Undefined function returns 0.
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://lore.kernel.org/r/20250428063034.2145566-8-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| 35ac2034 | 28-Apr-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Add support for AMD_SBI IOCTL
The present sbrmi module only support reporting power via hwmon. However, AMD data center range of processors support various system management functiona
misc: amd-sbi: Add support for AMD_SBI IOCTL
The present sbrmi module only support reporting power via hwmon. However, AMD data center range of processors support various system management functionality using custom protocols defined in Advanced Platform Management Link (APML) specification.
Register a miscdevice, which creates a device /dev/sbrmiX with an IOCTL interface for the user space to invoke the APML Mailbox protocol, which is already defined in sbrmi_mailbox_xfer().
The APML protocols depend on a set of RMI registers. Having an IOCTL as a single entry point will help in providing synchronization among these protocols as multiple transactions on RMI register set may create race condition. Support for other protocols will be added in subsequent patches.
APML mailbox protocol returns additional error codes written by SMU firmware in the out-bound register 0x37. These errors include, invalid core, message not supported over platform and others. This additional error codes can be used to provide more details to user space.
Open-sourced and widely used https://github.com/amd/esmi_oob_library will continue to provide user-space programmable API.
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://lore.kernel.org/r/20250428063034.2145566-7-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| 587d2c62 | 28-Apr-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Optimize the wait condition for mailbox command completion
- optimize the wait condition to indicate command completion by replacing the do while loop with regmap subsystem API re
misc: amd-sbi: Optimize the wait condition for mailbox command completion
- optimize the wait condition to indicate command completion by replacing the do while loop with regmap subsystem API regmap_read_poll_timeout()
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://lore.kernel.org/r/20250428063034.2145566-6-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| 013f7e71 | 28-Apr-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Use regmap subsystem
- regmap subsystem provides multiple benefits over direct smbus APIs - subsystem adds another abstraction layer on top of struct i2c_client to make it easy to r
misc: amd-sbi: Use regmap subsystem
- regmap subsystem provides multiple benefits over direct smbus APIs - subsystem adds another abstraction layer on top of struct i2c_client to make it easy to read or write registers. - The subsystem can be helpful in following cases - Different types of bus (i2c/i3c), we have plans to support i3c. - Different Register address size (1byte/2byte)
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://lore.kernel.org/r/20250428063034.2145566-5-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| f4dc6406 | 28-Apr-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Move hwmon device sensor as separate entity
- Move hwmon device sensor to misc as only power is reported through hwmon sensor.
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.
misc: amd-sbi: Move hwmon device sensor as separate entity
- Move hwmon device sensor to misc as only power is reported through hwmon sensor.
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://lore.kernel.org/r/20250428063034.2145566-4-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| 43470595 | 28-Apr-2025 |
Akshay Gupta <akshay.gupta@amd.com> |
misc: amd-sbi: Move protocol functionality to core file
- This is done to utilize the protocol functionality into other domains. - Increase the scalability of the module with different bus(i2c/i3c
misc: amd-sbi: Move protocol functionality to core file
- This is done to utilize the protocol functionality into other domains. - Increase the scalability of the module with different bus(i2c/i3c)
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://lore.kernel.org/r/20250428063034.2145566-3-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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