10c62c38 | 03-Jan-2025 |
Guo Ren <guoren@linux.alibaba.com> |
iommu/riscv: Fixup compile warning
When __BITS_PER_LONG == 32, size_t is defined as unsigned int rather than unsigned long. Therefore, we should use size_t to avoid type-checking errors.
Fixes: 488
iommu/riscv: Fixup compile warning
When __BITS_PER_LONG == 32, size_t is defined as unsigned int rather than unsigned long. Therefore, we should use size_t to avoid type-checking errors.
Fixes: 488ffbf18171 ("iommu/riscv: Paging domain support") Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org> Cc: Tomasz Jeznach <tjeznach@rivosinc.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Tomasz Jeznach <tjeznach@rivosinc.com> Link: https://lore.kernel.org/r/20250103024616.3359159-1-guoren@kernel.org Signed-off-by: Joerg Roedel <jroedel@suse.de>
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77a44196 | 03-Jan-2025 |
Xu Lu <luxu.kernel@bytedance.com> |
iommu/riscv: Add shutdown function for iommu driver
This commit supplies shutdown callback for iommu driver. The shutdown callback resets necessary registers so that newly booted kernel can pass ris
iommu/riscv: Add shutdown function for iommu driver
This commit supplies shutdown callback for iommu driver. The shutdown callback resets necessary registers so that newly booted kernel can pass riscv_iommu_init_check() after kexec. Also, the shutdown callback resets iommu mode to bare instead of off so that new kernel can still use PCIE devices even when CONFIG_RISCV_IOMMU is not enabled.
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com> Link: https://lore.kernel.org/r/20250103093220.38106-3-luxu.kernel@bytedance.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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8d8d3752 | 03-Jan-2025 |
Xu Lu <luxu.kernel@bytedance.com> |
iommu/riscv: Empty iommu queue before enabling it
Changing cqen/fqen/pqen from 0 to 1 sets the cqh/fqt/pqt registers to 0. But the cqt/fqh/pqh registers are left unmodified. This commit resets cqt/f
iommu/riscv: Empty iommu queue before enabling it
Changing cqen/fqen/pqen from 0 to 1 sets the cqh/fqt/pqt registers to 0. But the cqt/fqh/pqh registers are left unmodified. This commit resets cqt/fqh/pqh registers to ensure corresponding queues are empty before being enabled during initialization.
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com> Link: https://lore.kernel.org/r/20250103093220.38106-2-luxu.kernel@bytedance.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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488ffbf1 | 16-Oct-2024 |
Tomasz Jeznach <tjeznach@rivosinc.com> |
iommu/riscv: Paging domain support
Introduce first-stage address translation support.
Page table configured by the IOMMU driver will use the highest mode implemented by the hardware, unless not kno
iommu/riscv: Paging domain support
Introduce first-stage address translation support.
Page table configured by the IOMMU driver will use the highest mode implemented by the hardware, unless not known at the domain allocation time falling back to the CPU’s MMU page mode.
This change introduces IOTINVAL.VMA command, required to invalidate any cached IOATC entries after mapping is updated and/or removed from the paging domain. Invalidations for the non-leaf page entries use IOTINVAL for all addresses assigned to the protection domain for hardware not supporting more granular non-leaf page table cache invalidations.
Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/1109202d389f51c7121cb1460eb2f21429b9bd5d.1729059707.git.tjeznach@rivosinc.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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856c0cfe | 16-Oct-2024 |
Tomasz Jeznach <tjeznach@rivosinc.com> |
iommu/riscv: Command and fault queue support
Introduce device command submission and fault reporting queues, as described in Chapter 3.1 and 3.2 of the RISC-V IOMMU Architecture Specification.
Comm
iommu/riscv: Command and fault queue support
Introduce device command submission and fault reporting queues, as described in Chapter 3.1 and 3.2 of the RISC-V IOMMU Architecture Specification.
Command and fault queues are instantiated in contiguous system memory local to IOMMU device domain, or mapped from fixed I/O space provided by the hardware implementation. Detection of the location and maximum allowed size of the queue utilize WARL properties of queue base control register. Driver implementation will try to allocate up to 128KB of system memory, while respecting hardware supported maximum queue size.
Interrupts allocation is based on interrupt vectors availability and distributed to all queues in simple round-robin fashion. For hardware Implementation with fixed event type to interrupt vector assignment IVEC WARL property is used to discover such mappings.
Address translation, command and queue fault handling in this change is limited to simple fault reporting without taking any action.
Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/c4735fb6829053eff37ce1bcca4906192afd743c.1729059707.git.tjeznach@rivosinc.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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1bac10c5 | 16-Oct-2024 |
Tomasz Jeznach <tjeznach@rivosinc.com> |
iommu/riscv: Device directory management.
Introduce device context allocation and device directory tree management including capabilities discovery sequence, as described in Chapter 2.1 of the RISC-
iommu/riscv: Device directory management.
Introduce device context allocation and device directory tree management including capabilities discovery sequence, as described in Chapter 2.1 of the RISC-V IOMMU Architecture Specification.
Device directory mode will be auto detected using DDTP WARL property, using highest mode supported by the driver and hardware. If none supported can be configured, driver will fall back to global pass-through.
First level DDTP page can be located in I/O (detected using DDTP WARL) and system memory.
Only simple identity and blocking protection domains are supported by this implementation.
Co-developed-by: Nick Kossifidis <mick@ics.forth.gr> Signed-off-by: Nick Kossifidis <mick@ics.forth.gr> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/e1c763aeccd2c05fd4ad3a32f6f2ff3b3148d907.1729059707.git.tjeznach@rivosinc.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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822e8bc6 | 16-Oct-2024 |
Tomasz Jeznach <tjeznach@rivosinc.com> |
iommu/riscv: Enable IOMMU registration and device probe.
Advertise IOMMU device and its core API. Only minimal implementation for single identity domain type, without per-group domain protection.
R
iommu/riscv: Enable IOMMU registration and device probe.
Advertise IOMMU device and its core API. Only minimal implementation for single identity domain type, without per-group domain protection.
Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/ba79c8eb9c7f1cd9a8961a1b048e3991ee9a2b05.1729059707.git.tjeznach@rivosinc.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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68682e95 | 16-Oct-2024 |
Tomasz Jeznach <tjeznach@rivosinc.com> |
iommu/riscv: Add RISC-V IOMMU PCIe device driver
Introduce device driver for PCIe implementation of RISC-V IOMMU architected hardware.
IOMMU hardware and system support for MSI or MSI-X is required
iommu/riscv: Add RISC-V IOMMU PCIe device driver
Introduce device driver for PCIe implementation of RISC-V IOMMU architected hardware.
IOMMU hardware and system support for MSI or MSI-X is required by this implementation.
Vendor and device identifiers used in this patch matches QEMU implementation of the RISC-V IOMMU PCIe device, from Rivos VID (0x1efd) range allocated by the PCI-SIG.
MAINTAINERS | added iommu-pci.c already covered by matching pattern.
Link: https://lore.kernel.org/qemu-devel/20240307160319.675044-1-dbarboza@ventanamicro.com/ Co-developed-by: Nick Kossifidis <mick@ics.forth.gr> Signed-off-by: Nick Kossifidis <mick@ics.forth.gr> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/12f3bdbe519ebb7ca482191e7334d38b25b8ae8f.1729059707.git.tjeznach@rivosinc.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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