| cab40cfc | 19-Aug-2026 |
Jisheng Zhang <jszhang@kernel.org> |
i3c: dw: reduce do_daa time if there's no client
dw_i3c_master_daa() derives the number of newly assigned dynamic addresses from cmd->rx_len, the ISR sets it to the number of address slots ENTDAA le
i3c: dw: reduce do_daa time if there's no client
dw_i3c_master_daa() derives the number of newly assigned dynamic addresses from cmd->rx_len, the ISR sets it to the number of address slots ENTDAA left unassigned. It starts out as zero, which already means "every address was assigned", so a timed out transfer leaves that value in place and it gets used as a result.
If there's no client connected, the addr assign cmd times out, then the driver calls i3c_master_add_i3c_dev_locked() to add devices that are not there, each costing about 1s, thus adds non necessary boot time up to (maxdev * 1)s.
Start from maxdevs instead: no address is assigned before ENTDAA runs, and the existing rx_count >= maxdevs check then reports an empty bus.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260819044833.32611-1-jszhang@kernel.org Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| 455b454c | 18-Aug-2026 |
Jian-Ming Liao <Jm_Liao@asmedia.com.tw> |
i3c: mipi-i3c-hci: Add support for AMD_PT I3C controller
Add support for the AMD_PT I3C controller by introducing the following changes: - Add AMD_PT I3C controller platform device ID in core.c. - R
i3c: mipi-i3c-hci: Add support for AMD_PT I3C controller
Add support for the AMD_PT I3C controller by introducing the following changes: - Add AMD_PT I3C controller platform device ID in core.c. - Register AMD_PT I3C controller PCI ID in mipi-i3c-hci-pci.c.
Co-developed-by: Patrick Yen <Patrick_Yen@asmedia.com.tw> Signed-off-by: Patrick Yen <Patrick_Yen@asmedia.com.tw> Signed-off-by: Jian-Ming Liao <Jm_Liao@asmedia.com.tw> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260818104106.763772-4-Jm_Liao@asmedia.com.tw Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| ee53e178 | 18-Aug-2026 |
Jian-Ming Liao <Jm_Liao@asmedia.com.tw> |
i3c: mipi-i3c-hci: Add PIO queue management support for HCI v1.2
Support explicit enablement and starting of PIO queues as required by HCI v1.2. Handle alternate PIO queue sizes via ALT_QUEUE_SIZE r
i3c: mipi-i3c-hci: Add PIO queue management support for HCI v1.2
Support explicit enablement and starting of PIO queues as required by HCI v1.2. Handle alternate PIO queue sizes via ALT_QUEUE_SIZE register. Implement explicit PIO queue stopping/disabling and restart logic after errors.
Co-developed-by: Patrick Yen <Patrick_Yen@asmedia.com.tw> Signed-off-by: Patrick Yen <Patrick_Yen@asmedia.com.tw> Signed-off-by: Jian-Ming Liao <Jm_Liao@asmedia.com.tw> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260818104106.763772-3-Jm_Liao@asmedia.com.tw Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| 308ecb82 | 18-Aug-2026 |
Jian-Ming Liao <Jm_Liao@asmedia.com.tw> |
i3c: mipi-i3c-hci: Fix missing STAT_IBI_STATUS_THLD in PIO mode
In PIO mode initialization, STAT_IBI_STATUS_THLD was missing from pio->enabled_irqs. As a result, the host controller interrupt signal
i3c: mipi-i3c-hci: Fix missing STAT_IBI_STATUS_THLD in PIO mode
In PIO mode initialization, STAT_IBI_STATUS_THLD was missing from pio->enabled_irqs. As a result, the host controller interrupt signal for IBI threshold was never enabled when transfer starts, preventing IBI status descriptors from being properly processed in PIO mode.
Include STAT_IBI_STATUS_THLD in pio->enabled_irqs so that the IBI threshold interrupt is activated alongside error interrupts upon the first transfer.
Fixes: 9ad9a52cce28 ("i3c/master: introduce the mipi-i3c-hci driver") Co-developed-by: Patrick Yen <Patrick_Yen@asmedia.com.tw> Signed-off-by: Patrick Yen <Patrick_Yen@asmedia.com.tw> Signed-off-by: Jian-Ming Liao <Jm_Liao@asmedia.com.tw> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260818104106.763772-2-Jm_Liao@asmedia.com.tw Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| ff2eee2b | 14-Aug-2026 |
Jisheng Zhang <jszhang@kernel.org> |
i3c: dw: rename "pclk" to "apb" to match dt-binding
Change clock name "pclk" to "apb" to match dt-binding doc. No upstream device tree sources currently use the "pclk" clock name, so no any backward
i3c: dw: rename "pclk" to "apb" to match dt-binding
Change clock name "pclk" to "apb" to match dt-binding doc. No upstream device tree sources currently use the "pclk" clock name, so no any backward compatibility issues.
Fixes: a0d48ebf39ce ("i3c: dw: Add optional apb clock") Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260814040345.23033-1-jszhang@kernel.org Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| 9939e4cf | 13-Aug-2026 |
Jisheng Zhang <jszhang@kernel.org> |
i3c: dw: make struct dw_i3c_cmd smaller
The dw_i3c_cmd is dynamically allocated, make it smaller. For example on 64bit platforms, we reduce the size from 48 bytes to 32 bytes.
Signed-off-by: Jishen
i3c: dw: make struct dw_i3c_cmd smaller
The dw_i3c_cmd is dynamically allocated, make it smaller. For example on 64bit platforms, we reduce the size from 48 bytes to 32 bytes.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260813044603.22425-1-jszhang@kernel.org Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| 942e9a5b | 13-Aug-2026 |
Jisheng Zhang <jszhang@kernel.org> |
i3c: dw: use COMMAND_PORT_TRANSFER_ARG instead of hardcoding
Use the well defined COMMAND_PORT_TRANSFER_ARG macro instead of hardcoding '1'.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Review
i3c: dw: use COMMAND_PORT_TRANSFER_ARG instead of hardcoding
Use the well defined COMMAND_PORT_TRANSFER_ARG macro instead of hardcoding '1'.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260813044225.22237-1-jszhang@kernel.org Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| b6e56fd8 | 31-Jul-2026 |
Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> |
i3c: renesas: Don't register devices when ENTDAA times out
renesas_i3c_daa() derives the number of newly assigned dynamic addresses from cmd->rx_count, which the response ISR sets to the number of a
i3c: renesas: Don't register devices when ENTDAA times out
renesas_i3c_daa() derives the number of newly assigned dynamic addresses from cmd->rx_count, which the response ISR sets to the number of address slots ENTDAA left unassigned. It starts out as zero, which already means "every address was assigned", so a timed out transfer leaves that value in place and it gets used as a result.
On a bus with no target connected the ENTDAA times out and the driver registers RENESAS_I3C_MAX_DEVS devices that are not there, each costing the core two seconds on a GETPID that can only time out:
i3c i3c-0: Failed to add I3C device at address 9, error -110 ... i3c i3c-0: Failed to add I3C device at address 16, error -110
Start from maxdevs instead: no address is assigned before ENTDAA runs, and the existing rx_count >= maxdevs check then reports an empty bus.
Fixes: d028219a9f14 ("i3c: master: Add basic driver for the Renesas I3C controller") Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260731070150.2519825-1-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| 7315aad2 | 31-Jul-2026 |
Tze Yee Ng <tze.yee.ng@altera.com> |
i3c: master: dw-i3c-master: fix OD timing for first broadcast
Implement ->set_speed() so the I3C core can switch open-drain timing for the first broadcast address per spec: I3C_OPEN_DRAIN_SLOW_SPEED
i3c: master: dw-i3c-master: fix OD timing for first broadcast
Implement ->set_speed() so the I3C core can switch open-drain timing for the first broadcast address per spec: I3C_OPEN_DRAIN_SLOW_SPEED programs tHIGH_INIT (200 ns) before RSTDAA, and I3C_OPEN_DRAIN_NORMAL_SPEED restores normal OD timing afterward. Cache the normal OD register value during bus init and use a separate od_hcnt for the slow path so SDR extended timing remains derived from the normal PP hcnt.
For AMD_I3C_OD_PP_TIMING, cache AMD_I3C_OD_TIMING as the normal OD baseline and stop rewriting OD timing in send_ccc_cmd()/runtime resume so I3C_OPEN_DRAIN_SLOW_SPEED is preserved through RSTDAA.
Use PM_RUNTIME_ACQUIRE_AUTOSUSPEND() in set_speed(). Compute od_hcnt with DIV_ROUND_UP_ULL() for 32-bit safety and clamp it to U8_MAX to match the 8-bit I3C_OD_HCNT field.
Fixes I2C devices with spike filters not being detected on mixed buses.
Signed-off-by: Tze Yee Ng <tze.yee.ng@altera.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/d789219ca0418898a1ef2bf9295b4f96ca7b4209.1785484707.git.tze.yee.ng@altera.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| 1421e948 | 07-Aug-2026 |
Adrian Hunter <adrian.hunter@intel.com> |
i3c: mipi-i3c-hci: Advertise IBI wakeup capability
Set master->ibi_wakeup during probe when the associated system device advertises wakeup capability, allowing the I3C core to mark IBI-capable I3C d
i3c: mipi-i3c-hci: Advertise IBI wakeup capability
Set master->ibi_wakeup during probe when the associated system device advertises wakeup capability, allowing the I3C core to mark IBI-capable I3C devices as wakeup capable.
Tweak the comment for i3c_hci_sysdev() to mention the new usage.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260807145638.168865-15-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| 842e4692 | 07-Aug-2026 |
Adrian Hunter <adrian.hunter@intel.com> |
i3c: mipi-i3c-hci: Factor out i3c_hci_sysdev()
The MIPI I3C HCI driver needs to identify the underlying system device used for DMA mapping and PM operations. The logic for determining that device is
i3c: mipi-i3c-hci: Factor out i3c_hci_sysdev()
The MIPI I3C HCI driver needs to identify the underlying system device used for DMA mapping and PM operations. The logic for determining that device is currently embedded in the DMA implementation.
Factor this code out into i3c_hci_sysdev() so it can be shared by other parts of the driver and keep the device-selection logic in one place.
The explanatory comment moves with the code, reworked as kernel-doc now that it documents a function rather than an inline block.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Mukesh Savaliya <mukesh.savaliya@oss.qualcomm.com> Link: https://patch.msgid.link/20260807145638.168865-14-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| 94da8edf | 07-Aug-2026 |
Adrian Hunter <adrian.hunter@intel.com> |
i3c: mipi-i3c-hci-pci: Propagate I3C wakeup requirements to PCI
Keep the PCI wakeup state aligned with the wakeup requirements of the devices served by the controller(s).
The PCI function is the wa
i3c: mipi-i3c-hci-pci: Propagate I3C wakeup requirements to PCI
Keep the PCI wakeup state aligned with the wakeup requirements of the devices served by the controller(s).
The PCI function is the wakeup source for HCI instances exposed beneath it. However, wakeup is only needed when at least one attached I3C device is enabled as a wakeup source.
During suspend, check whether any HCI instance has a wakeup-enabled I3C device and enable wakeup for the PCI function only in that case. Otherwise leave PCI wakeup disabled.
Note, the suspend callback is used for both system and runtime suspend. Although this change may update the PCI wakeup state during runtime suspend, it does so only when the required wakeup state changes. Moreover, PCI wakeup-capable devices already have PME wakeup armed for runtime suspend, so changing the wakeup-enabled state does not affect runtime PM wakeup behavior.
Note also, since the PCI wakeup state is derived from the wakeup configuration of the attached I3C devices, the PCI device power/wakeup sysfs attribute no longer provides independent wakeup control.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260807145638.168865-13-adrian.hunter@intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| 2cdb9c21 | 21-Jul-2026 |
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> |
i3c: renesas: Drop unused structure member 'resuming'
The struct renesas_i3c::resuming is a leftover from a rebase. It is not used anywhere within the driver. Drop it.
Signed-off-by: Claudiu Beznea
i3c: renesas: Drop unused structure member 'resuming'
The struct renesas_i3c::resuming is a leftover from a rebase. It is not used anywhere within the driver. Drop it.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260721191618.1850795-1-claudiu.beznea+renesas@tuxon.dev Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| 97d7cfb6 | 28-Jul-2026 |
Akhil R <akhilrajeev@nvidia.com> |
i3c: dw-i3c-master: Add ACPI ID for Tegra410
Update variable names to generic names and add Tegra410 ACPI ID to support the I3C controller in Tegra410, which is a DesignWare I3C host controller.
Re
i3c: dw-i3c-master: Add ACPI ID for Tegra410
Update variable names to generic names and add Tegra410 ACPI ID to support the I3C controller in Tegra410, which is a DesignWare I3C host controller.
Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Link: https://patch.msgid.link/20260728065955.809445-10-akhilrajeev@nvidia.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| 0fd95499 | 28-Jul-2026 |
Akhil R <akhilrajeev@nvidia.com> |
i3c: dw-i3c-master: Add ACPI core clock frequency quirk
Some ACPI-enumerated devices like Tegra410 do not expose the controller core clock through the clk framework. Unlike device tree, ACPI on Arm
i3c: dw-i3c-master: Add ACPI core clock frequency quirk
Some ACPI-enumerated devices like Tegra410 do not expose the controller core clock through the clk framework. Unlike device tree, ACPI on Arm does not model clock providers. The hardware is expected to have its clocks enabled by firmware before the OS takes over.
Make the core clock optional and allow selected ACPI devices to provide the core clock rate through the "clock-frequency" _DSD property when the core clock is absent.
Resolve device quirks before acquiring the core clock so platforms without the ACPI skip-clock quirk still fail probe immediately when the clock is missing, before any MMIO access.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Link: https://patch.msgid.link/20260728065955.809445-9-akhilrajeev@nvidia.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| 52f6f5f4 | 20-Jul-2026 |
Shubham Patil <shubhamsanjay.patil@amd.com> |
i3c: master: dw: Drop redundant core reset name
The DesignWare I3C master has a single reset line, so a dedicated reset name is redundant. Look up the reset by index by passing NULL instead of the "
i3c: master: dw: Drop redundant core reset name
The DesignWare I3C master has a single reset line, so a dedicated reset name is redundant. Look up the reset by index by passing NULL instead of the "core_rst" name.
Signed-off-by: Shubham Patil <shubhamsanjay.patil@amd.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://patch.msgid.link/20260720073510.1869623-3-shubhamsanjay.patil@amd.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| a733069a | 15-Jul-2026 |
Can Peng <pengcan@kylinos.cn> |
i3c: master: adi: add OF module alias for autoloading
The Analog Devices I3C master driver can be built as a module and uses adi_i3c_master_of_match as its OF match table, but the table is not expor
i3c: master: adi: add OF module alias for autoloading
The Analog Devices I3C master driver can be built as a module and uses adi_i3c_master_of_match as its OF match table, but the table is not exported for module alias generation.
Add the MODULE_DEVICE_TABLE(of, ...) entry so modpost can generate OF module aliases for OF based module autoloading.
Fixes: a79ac2cdc91d ("i3c: master: Add driver for Analog Devices I3C Controller IP") Signed-off-by: Can Peng <pengcan@kylinos.cn> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260715012949.180245-1-pengcan@kylinos.cn Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| 4af1aacc | 13-Jul-2026 |
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> |
i3c: renesas: Add runtime PM support
On the SoCs where the Renesas I3C driver is enabled (RZ/G3S and RZ/G3E), the clocks of the IP are managed through a clock PM domain. To keep the I3C code simpler
i3c: renesas: Add runtime PM support
On the SoCs where the Renesas I3C driver is enabled (RZ/G3S and RZ/G3E), the clocks of the IP are managed through a clock PM domain. To keep the I3C code simpler, the explicit clock handling was dropped along with the addition of runtime PM support, in favor of the runtime PM APIs. Only the code for getting tclk was preserved, as it is necessary to compute the I3C clock rate.
All the APIs provided to the I3C subsystem through struct i3c_master_controller_ops are guarded with runtime PM APIs to enable/disable the controller at runtime.
As the Renesas I3C driver implements an asynchronous transmit model by preparing a transfer and waiting for its completion through the ISR, renesas_i3c_abort_xfer() was added to disable interrupts and clear any pending IRQ status bits when there is no completion in the defined timeout. Along with this, renesas_i3c_wait_xfer() return type was changed to unsigned long.
Add runtime PM support for the Renesas I3C driver.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Tested-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://patch.msgid.link/20260713130545.568657-18-claudiu.beznea+renesas@tuxon.dev Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| 46fa00a6 | 13-Jul-2026 |
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> |
i3c: renesas: Drop unnecessary tab
Remove an unnecessary tab to make the code cleaner.
Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Test
i3c: renesas: Drop unnecessary tab
Remove an unnecessary tab to make the code cleaner.
Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Tested-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://patch.msgid.link/20260713130545.568657-17-claudiu.beznea+renesas@tuxon.dev Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| 0c863015 | 13-Jul-2026 |
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> |
i3c: renesas: Use the "dev_name:irq_name" format for the interrupt name
Use the "dev_name:irq_name" format for the interrupt names. This makes it easier to identify interrupts in systems where multi
i3c: renesas: Use the "dev_name:irq_name" format for the interrupt name
Use the "dev_name:irq_name" format for the interrupt names. This makes it easier to identify interrupts in systems where multiple devices may request interrupts with the same name.
Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Tested-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://patch.msgid.link/20260713130545.568657-16-claudiu.beznea+renesas@tuxon.dev Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| 42a6f531 | 13-Jul-2026 |
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> |
i3c: renesas: Organize structures to avoid unnecessary padding
Reorder structure members to reduce padding and improve memory layout.
Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Claudiu
i3c: renesas: Organize structures to avoid unnecessary padding
Reorder structure members to reduce padding and improve memory layout.
Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Tested-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://patch.msgid.link/20260713130545.568657-15-claudiu.beznea+renesas@tuxon.dev Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| 826a7d3d | 13-Jul-2026 |
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> |
i3c: renesas: Update HW registers after SW computations are done
renesas_i3c_bus_init() performs a number of computations and software cache updates, interleaving them with hardware register writes.
i3c: renesas: Update HW registers after SW computations are done
renesas_i3c_bus_init() performs a number of computations and software cache updates, interleaving them with hardware register writes. While this works today, it makes it harder to minimize the time the controller must remain powered when runtime PM is introduced.
Perform all software computations and cache updates first, then update the hardware registers. This prepares for future runtime PM support.
Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Tested-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://patch.msgid.link/20260713130545.568657-14-claudiu.beznea+renesas@tuxon.dev Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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| 5e0b4ae8 | 13-Jul-2026 |
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> |
i3c: renesas: Drop the explicit memset() call
Drop the explicit memset() call on struct i3c_device_info object, as it is already initialized at declaration through compiler initialization.
Reviewed
i3c: renesas: Drop the explicit memset() call
Drop the explicit memset() call on struct i3c_device_info object, as it is already initialized at declaration through compiler initialization.
Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Tested-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://patch.msgid.link/20260713130545.568657-13-claudiu.beznea+renesas@tuxon.dev Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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