| #
c7fc0f37 |
| 05-Dec-2025 |
Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> |
drm/amd: Enable SMU 15_0_0 support
Add SMU 15_0_0
v2: rebase (Alex)
v3: fix clang build (Alex)
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Signed-off-by: Alex Deucher <alexander
drm/amd: Enable SMU 15_0_0 support
Add SMU 15_0_0
v2: rebase (Alex)
v3: fix clang build (Alex)
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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|
| #
fe6cd915 |
| 26-Apr-2023 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amd/swsmu: add smu14 ip support
Add initial swSMU support for smu 14 series ASIC.
v2: squash in build fixes and updates (Li Ma)
fix warnings (Alex)
v3: squash in updates (Alex)
v4: squash i
drm/amd/swsmu: add smu14 ip support
Add initial swSMU support for smu 14 series ASIC.
v2: squash in build fixes and updates (Li Ma)
fix warnings (Alex)
v3: squash in updates (Alex)
v4: squash in updates (Alex)
v5: squash in avg/current power updates (Alex)
Signed-off-by: Li Ma <li.ma@amd.com>
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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|
| #
c05d1c40 |
| 20-Oct-2020 |
Kevin Wang <kevin1.wang@amd.com> |
drm/amd/swsmu: add aldebaran smu13 ip support (v3)
Add initial swSMU support.
v1: add smu13 ip support for aldebaran asic (Kevin/Kenneth)
v2: switch to thm/mp v13_0 ip headers (Hawking)
v3: squash
drm/amd/swsmu: add aldebaran smu13 ip support (v3)
Add initial swSMU support.
v1: add smu13 ip support for aldebaran asic (Kevin/Kenneth)
v2: switch to thm/mp v13_0 ip headers (Hawking)
v3: squash in updates (Alex)
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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|
| #
e098bc96 |
| 13-Aug-2020 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: optimize the power related source code layout
The target is to provide a clear entry point(for power routines).
Also this can help to maintain a clear view about the frameworks
used on d
drm/amd/pm: optimize the power related source code layout
The target is to provide a clear entry point(for power routines).
Also this can help to maintain a clear view about the frameworks
used on different ASICs. Hopefully all these can make power part
more friendly to play with.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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|