drm/amd/display: Add P-State Keepout to dcn401 Global Sync[WHY&HOW]OTG has new functionality to allow P-State relative to VStartup. Keepout regionfor this should be configured based on DML output
drm/amd/display: Add P-State Keepout to dcn401 Global Sync[WHY&HOW]OTG has new functionality to allow P-State relative to VStartup. Keepout regionfor this should be configured based on DML outputs same as other global syncparams.Reviewed-by: Alvin Lee <alvin.lee2@amd.com>Signed-off-by: Jerry Zuo <jerry.zuo@amd.com>Signed-off-by: Dillon Varone <dillon.varone@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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drm/amd/display: Wait for double buffer update on ODM changes[WHAT & HOW]We must wait for ODM double buffer updates to completebefore exiting the pipe update sequence or we may reduceDISPCLK and
drm/amd/display: Wait for double buffer update on ODM changes[WHAT & HOW]We must wait for ODM double buffer updates to completebefore exiting the pipe update sequence or we may reduceDISPCLK and hit some transient underflow (pixel rate isreduced before the pipes have ODM enabled).Reviewed-by: Samson Tam <samson.tam@amd.com>Cc: Mario Limonciello <mario.limonciello@amd.com>Cc: Alex Deucher <alexander.deucher@amd.com>Cc: stable@vger.kernel.orgSigned-off-by: Alex Hung <alex.hung@amd.com>Signed-off-by: Alvin Lee <alvin.lee2@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Updated optc401_set_drr to use dcn401 functionswhy:optc_401_set_drr was using an old optc3 function to update vtotal min and max,causing crashes when disabling FAMS2how:Update
drm/amd/display: Updated optc401_set_drr to use dcn401 functionswhy:optc_401_set_drr was using an old optc3 function to update vtotal min and max,causing crashes when disabling FAMS2how:Updated dcn401 to point to opt401 function for vtotal updates. This version ofthe function has FAMS2 logic that allows for FAMS2 to be disabled.Reviewed-by: Dillon Varone <dillon.varone@amd.com>Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>Signed-off-by: Relja Vojvodic <relja.vojvodic@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add left edge pixel for YCbCr422/420 + ODM pipe split[WHY]Currently 3-tap chroma subsampling is used for YCbCr422/420. When ODMpipesplit is used, pixels on the left edge of ODM s
drm/amd/display: Add left edge pixel for YCbCr422/420 + ODM pipe split[WHY]Currently 3-tap chroma subsampling is used for YCbCr422/420. When ODMpipesplit is used, pixels on the left edge of ODM slices need one extrapixel from the right edge of the previous slice to calculate the correctchroma value.Without this change, the chroma value is slightly different thanexpected. This is usually imperceptible visually, but it impacts testpattern CRCs for compliance test automation.[HOW]Update logic to use the register for adding extra left edge pixel forYCbCr422/420 ODM cases.Reviewed-by: George Shen <george.shen@amd.com>Acked-by: Alex Hung <alex.hung@amd.com>Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: reset DSC clock in post unlock update[why]Switching between DSC clock or disable DSC block are not double buffered update.Corruption is observed if these updates happen before DS
drm/amd/display: reset DSC clock in post unlock update[why]Switching between DSC clock or disable DSC block are not double buffered update.Corruption is observed if these updates happen before DSC double buffereddisconnection.[how]Move DSC disable and refclk reset to post unlock update. Wait for DSC double buffereddisconnection and all mpccs are disconnected before reset DSC clock.Reviewed-by: Samson Tam <samson.tam@amd.com>Acked-by: Tom Chung <chiahsuan.chung@amd.com>Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: use even ODM slice width for two pixels per container[why]When optc uses two pixel per container, each ODM slice width must be aneven number.[how]If ODM slice width is odd num
drm/amd/display: use even ODM slice width for two pixels per container[why]When optc uses two pixel per container, each ODM slice width must be aneven number.[how]If ODM slice width is odd number increase it by 1.Reviewed-by: Dillon Varone <dillon.varone@amd.com>Acked-by: Wayne Lin <wayne.lin@amd.com>Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Address kdoc for 'Enable CRTC' in optc401_enable_crtcThis commit fixes the kdoc for 'Enable CRTC' in `optc401_enable_crtc`function.Fixes the below with gcc W=1:drivers/gpu/drm/
drm/amd/display: Address kdoc for 'Enable CRTC' in optc401_enable_crtcThis commit fixes the kdoc for 'Enable CRTC' in `optc401_enable_crtc`function.Fixes the below with gcc W=1:drivers/gpu/drm/amd/amdgpu/../display/dc/optc/dcn401/dcn401_optc.c:177: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Enable CRTCFixes: 70839da63605 ("drm/amd/display: Add new DCN401 sources")Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>Cc: Roman Li <roman.li@amd.com>Cc: Qingqing Zhuo <Qingqing.Zhuo@amd.com>Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>Cc: Tom Chung <chiahsuan.chung@amd.com>Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>Reviewed-by: Tom Chung <chiahsuan.chung@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add new DCN401 sourcesAdd initial support for DCN 4.0.1.Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>Signed-of
drm/amd/display: Add new DCN401 sourcesAdd initial support for DCN 4.0.1.Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>