drm/amd/display: replace fast_validate with enum dc_validate_mode[Why]The boolean fast_validate is used as aninput parameter in multiple functions. Tosupport more scenarios, we arereplacing it
drm/amd/display: replace fast_validate with enum dc_validate_mode[Why]The boolean fast_validate is used as aninput parameter in multiple functions. Tosupport more scenarios, we arereplacing it with enum dc_validate_mode.[How]The enum dc_validate_mode introduces threepossible values:1) DC_VALIDATE_MODE_AND_PROGRAMMING: Apply the mode to hardware2) DC_VALIDATE_MODE_ONLY: Check whether the mode can be supported3) DC_VALIDATE_MODE_AND_STATE_INDEX: Check if the mode can be supported, and determine the optimal voltage level needed to support it.Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>Signed-off-by: Yan Li <yan.li@amd.com>Signed-off-by: Wayne Lin <wayne.lin@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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drm/amd/display: pass calculated dram_speed_mts to dml2[why]currently dml2 is using a hard coded 16 to convert memclk to dram_speed_mts.for apu, this depends on wck_ratio.change to pass the alr
drm/amd/display: pass calculated dram_speed_mts to dml2[why]currently dml2 is using a hard coded 16 to convert memclk to dram_speed_mts.for apu, this depends on wck_ratio.change to pass the already calculated dram_speed_mts from fpu to dml2.v2: use existing calculation of dram_speed_mts for now to avoid regressionSigned-off-by: Charlene Liu <Charlene.Liu@amd.com>Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>Reviewed-by: Roman Li <Roman.Li@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: update sr_exit latency for z8This is based on real asic performance result.Reviewed-by: Alvin Lee <alvin.lee2@amd.com>Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>Signed-o
drm/amd/display: update sr_exit latency for z8This is based on real asic performance result.Reviewed-by: Alvin Lee <alvin.lee2@amd.com>Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Change dram_clock_latency to 34us for dcn351[Why]Intermittent underflow observed when using 4k144 display ondcn351[How]Update dram_clock_change_latency_us from 11.72us to 34us
drm/amd/display: Change dram_clock_latency to 34us for dcn351[Why]Intermittent underflow observed when using 4k144 display ondcn351[How]Update dram_clock_change_latency_us from 11.72us to 34usReviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>Signed-off-by: Daniel Miess <daniel.miess@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: delete the redundant initialization in dcn3_51_socthe dram_clock_change_latency_us in dcn3_51_soc is initialized twice, sodelete one of them.Acked-by: Alex Deucher <alexander.de
drm/amd/display: delete the redundant initialization in dcn3_51_socthe dram_clock_change_latency_us in dcn3_51_soc is initialized twice, sodelete one of them.Acked-by: Alex Deucher <alexander.deucher@amd.com>Signed-off-by: Xiang Yang <xiangyang3@huawei.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Fix compiler warnings on high compiler warning levels[why]Enabling higher compiler warning levels results in many issues that canbe trivially resolved as well as some potentially
drm/amd/display: Fix compiler warnings on high compiler warning levels[why]Enabling higher compiler warning levels results in many issues that canbe trivially resolved as well as some potentially critical issues.[how]Fix all compiler warnings found with various compilers and higherwarning levels. Primarily, potentially uninitialized variables andunreachable code.Reviewed-by: Leo Li <sunpeng.li@amd.com>Acked-by: Roman Li <roman.li@amd.com>Signed-off-by: Aric Cyr <aric.cyr@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Update dcn351 to latest dcn35 config[why & how]There were some fixes in dcn35 that needto be ported over to dcn351 to prevent anyregression.Signed-off-by: Sung Joon Kim <sungk
drm/amd/display: Update dcn351 to latest dcn35 config[why & how]There were some fixes in dcn35 that needto be ported over to dcn351 to prevent anyregression.Signed-off-by: Sung Joon Kim <sungkim@amd.com>Reviewed-by: Liu, Xi (Alex) <xiliu102@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: increase bb clock for DCN351[Why and how]Bounding box clocks for DCN351 should be increased as per requestReviewed-by: Swapnil Patel <swapnil.patel@amd.com>Acked-by: Wayne Lin
drm/amd/display: increase bb clock for DCN351[Why and how]Bounding box clocks for DCN351 should be increased as per requestReviewed-by: Swapnil Patel <swapnil.patel@amd.com>Acked-by: Wayne Lin <wayne.lin@amd.com>Signed-off-by: Xi Liu <xi.liu@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Increase Z8 watermark times.Increase Z8 watermark times from 210->250us and 320->350us.Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>Acked-by: Wayne Lin <wayne.l
drm/amd/display: Increase Z8 watermark times.Increase Z8 watermark times from 210->250us and 320->350us.Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>Acked-by: Wayne Lin <wayne.lin@amd.com>Signed-off-by: Natanel Roizenman <natanel.roizenman@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: add DC changes for DCN351Add DC support for DCN 3.5.1.Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>