| a612d3d6 | 14-Feb-2026 |
Stephen Boyd <sboyd@kernel.org> |
Merge branches 'clk-imx', 'clk-divider', 'clk-rockchip' and 'clk-microchip' into clk-next
* clk-imx:
clk: imx: fracn-gppll: Add 241.90 MHz Support
clk: imx: fracn-gppll: Add 332.60 MHz Support
Merge branches 'clk-imx', 'clk-divider', 'clk-rockchip' and 'clk-microchip' into clk-next
* clk-imx:
clk: imx: fracn-gppll: Add 241.90 MHz Support
clk: imx: fracn-gppll: Add 332.60 MHz Support
* clk-divider:
rtc: ac100: convert from divider_round_rate() to divider_determine_rate()
clk: zynqmp: divider: convert from divider_round_rate() to divider_determine_rate()
clk: x86: cgu: convert from divider_round_rate() to divider_determine_rate()
clk: versaclock3: convert from divider_round_rate() to divider_determine_rate()
clk: stm32: stm32-core: convert from divider_round_rate_parent() to divider_determine_rate()
clk: stm32: stm32-core: convert from divider_ro_round_rate() to divider_ro_determine_rate()
clk: sprd: div: convert from divider_round_rate() to divider_determine_rate()
clk: sophgo: sg2042-clkgen: convert from divider_round_rate() to divider_determine_rate()
clk: nxp: lpc32xx: convert from divider_round_rate() to divider_determine_rate()
clk: nuvoton: ma35d1-divider: convert from divider_round_rate() to divider_determine_rate()
clk: milbeaut: convert from divider_round_rate() to divider_determine_rate()
clk: milbeaut: convert from divider_ro_round_rate() to divider_ro_determine_rate()
clk: loongson1: convert from divider_round_rate() to divider_determine_rate()
clk: hisilicon: clkdivider-hi6220: convert from divider_round_rate() to divider_determine_rate()
clk: bm1880: convert from divider_round_rate() to divider_determine_rate()
clk: bm1880: convert from divider_ro_round_rate() to divider_ro_determine_rate()
clk: actions: owl-divider: convert from divider_round_rate() to divider_determine_rate()
clk: actions: owl-composite: convert from owl_divider_helper_round_rate() to divider_determine_rate()
clk: sunxi-ng: convert from divider_round_rate_parent() to divider_determine_rate()
clk: sophgo: cv18xx-ip: convert from divider_round_rate() to divider_determine_rate()
* clk-rockchip:
clk: rockchip: Fix error pointer check after rockchip_clk_register_gate_link()
* clk-microchip:
dt-bindings: clock: mpfs-clkcfg: Add pic64gx compatibility
dt-bindings: clock: mpfs-ccc: Add pic64gx compatibility
clk: microchip: drop POLARFIRE from ARCH_MICROCHIP_POLARFIRE
clk: microchip: core: remove unused include asm/traps.h
clk: microchip: core: correct return value on *_get_parent()
clk: microchip: core: remove duplicate determine_rate on pic32_sclk_ops
show more ...
/linux/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml/linux/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml/linux/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml/linux/Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml/linux/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml/linux/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml/linux/Documentation/devicetree/bindings/clock/renesas,9series.yaml/linux/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml/linux/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml/linux/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml/linux/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml/linux/drivers/clk/.kunitconfig/linux/drivers/clk/actions/owl-composite.c/linux/drivers/clk/actions/owl-divider.c/linux/drivers/clk/actions/owl-divider.h/linux/drivers/clk/clk-bm1880.c/linux/drivers/clk/clk-loongson1.c/linux/drivers/clk/clk-milbeaut.c/linux/drivers/clk/clk-renesas-pcie.c/linux/drivers/clk/clk-versaclock3.c/linux/drivers/clk/hisilicon/clkdivider-hi6220.c/linux/drivers/clk/imx/clk-fracn-gppll.c/linux/drivers/clk/mediatek/Kconfig/linux/drivers/clk/mediatek/clk-mt2701.c/linux/drivers/clk/mediatek/clk-mt2712-apmixedsys.c/linux/drivers/clk/mediatek/clk-mt6735-apmixedsys.c/linux/drivers/clk/mediatek/clk-mt6765.c/linux/drivers/clk/mediatek/clk-mt6779.c/linux/drivers/clk/mediatek/clk-mt6795-apmixedsys.c/linux/drivers/clk/mediatek/clk-mt6797.c/linux/drivers/clk/mediatek/clk-mt7622-apmixedsys.c/linux/drivers/clk/mediatek/clk-mt7629.c/linux/drivers/clk/mediatek/clk-mt7981-apmixed.c/linux/drivers/clk/mediatek/clk-mt7981-eth.c/linux/drivers/clk/mediatek/clk-mt7986-apmixed.c/linux/drivers/clk/mediatek/clk-mt7988-apmixed.c/linux/drivers/clk/mediatek/clk-mt8135-apmixedsys.c/linux/drivers/clk/mediatek/clk-mt8167-apmixedsys.c/linux/drivers/clk/mediatek/clk-mt8173-apmixedsys.c/linux/drivers/clk/mediatek/clk-mt8183-apmixedsys.c/linux/drivers/clk/mediatek/clk-mt8186-apmixedsys.c/linux/drivers/clk/mediatek/clk-mt8188-apmixedsys.c/linux/drivers/clk/mediatek/clk-mt8192-apmixedsys.c/linux/drivers/clk/mediatek/clk-mt8195-apmixedsys.c/linux/drivers/clk/mediatek/clk-mt8195-apusys_pll.c/linux/drivers/clk/mediatek/clk-mt8196-apmixedsys.c/linux/drivers/clk/mediatek/clk-mt8196-mcu.c/linux/drivers/clk/mediatek/clk-mt8196-mfg.c/linux/drivers/clk/mediatek/clk-mt8196-vlpckgen.c/linux/drivers/clk/mediatek/clk-mt8365-apmixedsys.c/linux/drivers/clk/mediatek/clk-mt8516-apmixedsys.c/linux/drivers/clk/mediatek/clk-mt8516.c/linux/drivers/clk/mediatek/clk-mtk.c/linux/drivers/clk/mediatek/clk-pll.c/linux/drivers/clk/mediatek/clk-pll.h/linux/drivers/clk/mediatek/clk-pllfh.c/linux/drivers/clk/mediatek/clk-pllfh.h/linux/drivers/clk/meson/Kconfig/linux/drivers/clk/meson/Makefile/linux/drivers/clk/meson/g12a.c/linux/drivers/clk/meson/gxbb.c/linux/drivers/clk/meson/s4-peripherals.c/linux/drivers/clk/meson/t7-peripherals.c/linux/drivers/clk/meson/t7-pll.c/linux/drivers/clk/microchip/Kconfig/linux/drivers/clk/microchip/clk-core.c/linux/drivers/clk/nuvoton/clk-ma35d1-divider.c/linux/drivers/clk/nxp/clk-lpc32xx.c/linux/drivers/clk/renesas/clk-vbattb.c/linux/drivers/clk/renesas/r9a09g056-cpg.c/linux/drivers/clk/renesas/r9a09g057-cpg.c/linux/drivers/clk/renesas/r9a09g077-cpg.c/linux/drivers/clk/renesas/renesas-cpg-mssr.c/linux/drivers/clk/renesas/rzg2l-cpg.c/linux/drivers/clk/renesas/rzv2h-cpg.c/linux/drivers/clk/rockchip/clk.c/linux/drivers/clk/samsung/clk-exynos-arm64.c/linux/drivers/clk/samsung/clk-exynos4.c/linux/drivers/clk/samsung/clk-exynos4412-isp.c/linux/drivers/clk/samsung/clk-exynos5250.c/linux/drivers/clk/samsung/clk-exynos5420.c/linux/drivers/clk/samsung/clk-exynosautov920.c/linux/drivers/clk/samsung/clk-gs101.c/linux/drivers/clk/samsung/clk-s3c64xx.c/linux/drivers/clk/samsung/clk-s5pv210.c/linux/drivers/clk/samsung/clk.c/linux/drivers/clk/samsung/clk.h/linux/drivers/clk/sophgo/clk-cv18xx-ip.c/linux/drivers/clk/sophgo/clk-sg2042-clkgen.c/linux/drivers/clk/spacemit/Kconfig/linux/drivers/clk/spacemit/Makefile/linux/drivers/clk/spacemit/ccu-k1.c/linux/drivers/clk/spacemit/ccu-k3.c/linux/drivers/clk/spacemit/ccu_common.c/linux/drivers/clk/spacemit/ccu_common.h/linux/drivers/clk/spacemit/ccu_ddn.c/linux/drivers/clk/spacemit/ccu_mix.c/linux/drivers/clk/spacemit/ccu_mix.h/linux/drivers/clk/spacemit/ccu_pll.c/linux/drivers/clk/spacemit/ccu_pll.h/linux/drivers/clk/sprd/div.c/linux/drivers/clk/stm32/clk-stm32-core.c/linux/drivers/clk/sunxi-ng/ccu_div.c/linux/drivers/clk/sunxi-ng/ccu_mp.c/linux/drivers/clk/sunxi-ng/ccu_mult.c/linux/drivers/clk/sunxi-ng/ccu_mux.c/linux/drivers/clk/sunxi-ng/ccu_mux.h/linux/drivers/clk/sunxi-ng/ccu_nkm.c/linux/drivers/clk/tegra/clk-device.c/linux/drivers/clk/tegra/clk-tegra114.c/linux/drivers/clk/tegra/clk-tegra124-emc.c/linux/drivers/clk/tegra/clk-tegra20.c/linux/drivers/clk/tegra/clk-tegra30.c/linux/drivers/clk/thead/clk-th1520-ap.c/linux/drivers/clk/x86/clk-cgu.cdivider.c/linux/drivers/reset/reset-spacemit.c/linux/drivers/rtc/rtc-ac100.c/linux/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h/linux/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h/linux/include/dt-bindings/clock/amlogic,t7-pll-clkc.h/linux/include/dt-bindings/clock/amlogic,t7-scmi.h/linux/include/dt-bindings/clock/google,gs101.h/linux/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h/linux/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h/linux/include/dt-bindings/clock/samsung,exynosautov920.h/linux/include/dt-bindings/clock/spacemit,k3-clocks.h/linux/include/dt-bindings/clock/thead,th1520-clk-ap.h/linux/include/linux/clk/renesas.h/linux/include/soc/spacemit/ccu.h/linux/include/soc/spacemit/k1-syscon.h/linux/include/soc/spacemit/k3-syscon.h |
| 750e0e0a | 24-Dec-2025 |
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> |
clk: zynqmp: pll: Fix zynqmp_clk_divider_determine_rate kerneldoc
After renaming round_rate->determine, kerneldoc does not match anymore,
causing W=1 warnings:
pll.c:102 function parameter 'req'
clk: zynqmp: pll: Fix zynqmp_clk_divider_determine_rate kerneldoc
After renaming round_rate->determine, kerneldoc does not match anymore,
causing W=1 warnings:
pll.c:102 function parameter 'req' not described in 'zynqmp_pll_determine_rate'
pll.c:102 expecting prototype for zynqmp_pll_round_rate(). Prototype was for zynqmp_pll_determine_rate() instead
Fixes: 193650c7a873 ("clk: zynqmp: pll: convert from round_rate() to determine_rate()")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
|
| 1fe15be1 | 29-Nov-2023 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
drivers: clk: zynqmp: update divider round rate logic
Currently zynqmp divider round rate is considering single parent and
calculating rate and parent rate accordingly. But if divider clock flag
is
drivers: clk: zynqmp: update divider round rate logic
Currently zynqmp divider round rate is considering single parent and
calculating rate and parent rate accordingly. But if divider clock flag
is set to SET_RATE_PARENT then its not trying to traverse through all
parent rate and not selecting best parent rate from that. So use common
divider_round_rate() which is traversing through all clock parents and
its rate and calculating proper parent rate.
Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver")
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Link: https://lore.kernel.org/r/20231129112916.23125-3-jay.buddhabhatti@amd.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
|
| 30eaf021 | 26-Aug-2022 |
Quanyang Wang <quanyang.wang@windriver.com> |
clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round_rate
The function zynqmp_pll_round_rate is used to find a most appropriate
PLL frequency which the hardware can generate according to the
clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round_rate
The function zynqmp_pll_round_rate is used to find a most appropriate
PLL frequency which the hardware can generate according to the desired
frequency. For example, if the desired frequency is 297MHz, considering
the limited range from PS_PLL_VCO_MIN (1.5GHz) to PS_PLL_VCO_MAX (3.0GHz)
of PLL, zynqmp_pll_round_rate should return 1.872GHz (297MHz * 5).
There are two problems with the current code of zynqmp_pll_round_rate:
1) When the rate is below PS_PLL_VCO_MIN, it can't find a correct rate
when the parameter "rate" is an integer multiple of *prate, in other words,
if "f" is zero, zynqmp_pll_round_rate won't return a valid frequency which
is from PS_PLL_VCO_MIN to PS_PLL_VCO_MAX. For example, *prate is 33MHz
and the rate is 660MHz, zynqmp_pll_round_rate will not boost up rate and
just return 660MHz, and this will cause clk_calc_new_rates failure since
zynqmp_pll_round_rate returns an invalid rate out of its boundaries.
2) Even if the rate is higher than PS_PLL_VCO_MIN, there is still a risk
that zynqmp_pll_round_rate returns an invalid rate because the function
DIV_ROUND_CLOSEST makes some loss in the fractional part. If the parent
clock *prate is 33333333Hz and we want to set the PLL rate to 1.5GHz,
this function will return 1499999985Hz by using the formula below:
value = *prate * DIV_ROUND_CLOSEST(rate, *prate)).
This value is also invalid since it's slightly smaller than PS_PLL_VCO_MIN.
because DIV_ROUND_CLOSEST makes some loss in the fractional part.
Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
Link: https://lore.kernel.org/r/20220826142030.213805-1-quanyang.wang@windriver.com
Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
|
| 8bdb15cd | 06-Apr-2022 |
Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> |
clk: zynqmp: Check the return type zynqmp_pm_query_data
Check the return type of zynqmp_pm_query_data(qdata, ret_payload);
Addresses-Coverity: Event check_return
Signed-off-by: Shubhrajyoti Datta <
clk: zynqmp: Check the return type zynqmp_pm_query_data
Check the return type of zynqmp_pm_query_data(qdata, ret_payload);
Addresses-Coverity: Event check_return
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.org/r/20220406092211.19017-1-shubhrajyoti.datta@xilinx.com
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
|
| 6ab9810c | 18-May-2022 |
Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> |
clk: zynqmp: Add a check for NULL pointer
Add a NULL pointer check as clk_hw_get_parent can return NULL.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.
clk: zynqmp: Add a check for NULL pointer
Add a NULL pointer check as clk_hw_get_parent can return NULL.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.org/r/20220518055314.2486-1-shubhrajyoti.datta@xilinx.com
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
|
| acc1c732 | 10-May-2022 |
Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> |
clk: zynqmp: Replaced strncpy() with strscpy()
Replaced strncpy() with strscpy() as the clock names are supposed to
be NULL terminated.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.
clk: zynqmp: Replaced strncpy() with strscpy()
Replaced strncpy() with strscpy() as the clock names are supposed to
be NULL terminated.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.org/r/20220510070154.29528-2-shubhrajyoti.datta@xilinx.com
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
|
| dd80fb2d | 10-May-2022 |
Ian Nam <young.kwan.nam@xilinx.com> |
clk: zynqmp: Fix stack-out-of-bounds in strncpy`
"BUG: KASAN: stack-out-of-bounds in strncpy+0x30/0x68"
Linux-ATF interface is using 16 bytes of SMC payload. In case clock name is
longer than 15 by
clk: zynqmp: Fix stack-out-of-bounds in strncpy`
"BUG: KASAN: stack-out-of-bounds in strncpy+0x30/0x68"
Linux-ATF interface is using 16 bytes of SMC payload. In case clock name is
longer than 15 bytes, string terminated NULL character will not be received
by Linux. Add explicit NULL character at last byte to fix issues when clock
name is longer.
This fixes below bug reported by KASAN:
==================================================================
BUG: KASAN: stack-out-of-bounds in strncpy+0x30/0x68
Read of size 1 at addr ffff0008c89a7410 by task swapper/0/1
CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.4.0-00396-g81ef9e7-dirty #3
Hardware name: Xilinx Versal vck190 Eval board revA (QSPI) (DT)
Call trace:
dump_backtrace+0x0/0x1e8
show_stack+0x14/0x20
dump_stack+0xd4/0x108
print_address_description.isra.0+0xbc/0x37c
__kasan_report+0x144/0x198
kasan_report+0xc/0x18
__asan_load1+0x5c/0x68
strncpy+0x30/0x68
zynqmp_clock_probe+0x238/0x7b8
platform_drv_probe+0x6c/0xc8
really_probe+0x14c/0x418
driver_probe_device+0x74/0x130
__device_attach_driver+0xc4/0xe8
bus_for_each_drv+0xec/0x150
__device_attach+0x160/0x1d8
device_initial_probe+0x10/0x18
bus_probe_device+0xe0/0xf0
device_add+0x528/0x950
of_device_add+0x5c/0x80
of_platform_device_create_pdata+0x120/0x168
of_platform_bus_create+0x244/0x4e0
of_platform_populate+0x50/0xe8
zynqmp_firmware_probe+0x370/0x3a8
platform_drv_probe+0x6c/0xc8
really_probe+0x14c/0x418
driver_probe_device+0x74/0x130
device_driver_attach+0x94/0xa0
__driver_attach+0x70/0x108
bus_for_each_dev+0xe4/0x158
driver_attach+0x30/0x40
bus_add_driver+0x21c/0x2b8
driver_register+0xbc/0x1d0
__platform_driver_register+0x7c/0x88
zynqmp_firmware_driver_init+0x1c/0x24
do_one_initcall+0xa4/0x234
kernel_init_freeable+0x1b0/0x24c
kernel_init+0x10/0x110
ret_from_fork+0x10/0x18
The buggy address belongs to the page:
page:ffff0008f9be1c88 refcount:0 mapcount:0 mapping:0000000000000000 index:0x0
raw: 0008d00000000000 ffff0008f9be1c90 ffff0008f9be1c90 0000000000000000
raw: 0000000000000000 0000000000000000 00000000ffffffff
page dumped because: kasan: bad access detected
addr ffff0008c89a7410 is located in stack of task swapper/0/1 at offset 112 in frame:
zynqmp_clock_probe+0x0/0x7b8
this frame has 3 objects:
[32, 44) 'response'
[64, 80) 'ret_payload'
[96, 112) 'name'
Memory state around the buggy address:
ffff0008c89a7300: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
ffff0008c89a7380: 00 00 00 00 f1 f1 f1 f1 00 04 f2 f2 00 00 f2 f2
>ffff0008c89a7400: 00 00 f3 f3 00 00 00 00 00 00 00 00 00 00 00 00
^
ffff0008c89a7480: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
ffff0008c89a7500: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
==================================================================
Signed-off-by: Ian Nam <young.kwan.nam@xilinx.com>
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.org/r/20220510070154.29528-3-shubhrajyoti.datta@xilinx.com
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
|
| 6e1cc688 | 23-Aug-2021 |
Michal Simek <michal.simek@xilinx.com> |
clk: zynqmp: Fix kernel-doc format
Align structure and function names with definitions.
Issues are reported by kernel-doc script as:
drivers/clk/zynqmp/clk-gate-zynqmp.c:24: warning: expecting prot
clk: zynqmp: Fix kernel-doc format
Align structure and function names with definitions.
Issues are reported by kernel-doc script as:
drivers/clk/zynqmp/clk-gate-zynqmp.c:24: warning: expecting prototype for
struct clk_gate. Prototype was for struct zynqmp_clk_gate instead
drivers/clk/zynqmp/clk-gate-zynqmp.c:75: warning: expecting prototype for
zynqmp_clk_gate_is_enable(). Prototype was for zynqmp_clk_gate_is_enabled()
instead
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/26526e144296373b2c75e75865dd023158f9bfc7.1629718424.git.michal.simek@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
|
| e7296d16 | 18-Aug-2021 |
Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> |
clk: zynqmp: Fix a memory leak
Fix a memory leak of mux.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.org/r/20210818065929.12835-3-shubhrajyoti.datta@
clk: zynqmp: Fix a memory leak
Fix a memory leak of mux.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.org/r/20210818065929.12835-3-shubhrajyoti.datta@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
|