clk: Fix typosFix typos, mostly in comments except CLKGATE_SEPERATED_* (definition anduses updated).Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>Link: https://lore.kernel.org/r/20250723203
clk: Fix typosFix typos, mostly in comments except CLKGATE_SEPERATED_* (definition anduses updated).Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>Link: https://lore.kernel.org/r/20250723203819.2910289-1-helgaas@kernel.orgSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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clk: sophgo: Use div64* for 64-by-32 division to simplifyFixes Coccinelle/coccicheck warnings reported by do_div.cocci.cocci warnings: drivers/clk/sophgo/clk-sg2042-pll.c:217:1-7: WARNING:
clk: sophgo: Use div64* for 64-by-32 division to simplifyFixes Coccinelle/coccicheck warnings reported by do_div.cocci.cocci warnings: drivers/clk/sophgo/clk-sg2042-pll.c:217:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead. drivers/clk/sophgo/clk-sg2042-pll.c:160:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_u64 instead.replace do_div() with div64_*() which doesn't implicitly cast the divisor.Signed-off-by: Pei Xiao <xiaopei01@kylinos.cn>Link: https://lore.kernel.org/r/tencent_D5D35C992B70843CF70F5533E49717D24906@qq.comReviewed-by: Inochi Amaoto <inochiama@gmail.com>Reviewed-by: Chen Wang <wangchen20@iscas.ac.cn>Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: sophgo: Add clock controller support for SG2044 SoCAdd clock driver and clock definition for SG2044 SoC.Reviewed-by: Chen Wang <unicorn_wang@outlook.com>Link: https://lore.kernel.org/r/2025
clk: sophgo: Add clock controller support for SG2044 SoCAdd clock driver and clock definition for SG2044 SoC.Reviewed-by: Chen Wang <unicorn_wang@outlook.com>Link: https://lore.kernel.org/r/20250418020325.421257-6-inochiama@gmail.comSigned-off-by: Inochi Amaoto <inochiama@gmail.com>Signed-off-by: Chen Wang <unicorn_wang@outlook.com>Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
clk: sophgo: Add PLL clock controller support for SG2044 SoCAdd PLL clock driver and clock definition for SG2044 SoC.Link: https://lore.kernel.org/r/20250418020325.421257-5-inochiama@gmail.comSi
clk: sophgo: Add PLL clock controller support for SG2044 SoCAdd PLL clock driver and clock definition for SG2044 SoC.Link: https://lore.kernel.org/r/20250418020325.421257-5-inochiama@gmail.comSigned-off-by: Inochi Amaoto <inochiama@gmail.com>Signed-off-by: Chen Wang <unicorn_wang@outlook.com>Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
clk: sophgo: Add support for newly added precise compatibleAdd of device id definition for newly added precise compatible.Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>Link: http
clk: sophgo: Add support for newly added precise compatibleAdd of device id definition for newly added precise compatible.Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>Link: https://lore.kernel.org/r/20250504104553.1447819-3-inochiama@gmail.comSigned-off-by: Inochi Amaoto <inochiama@gmail.com>Signed-off-by: Chen Wang <unicorn_wang@outlook.com>Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
clk: sophgo: avoid integer overflow in sg2042_pll_recalc_rate()This was found by a static analyzer.There may be a potential integer overflow issue insg2042_pll_recalc_rate(). numerator is defined
clk: sophgo: avoid integer overflow in sg2042_pll_recalc_rate()This was found by a static analyzer.There may be a potential integer overflow issue insg2042_pll_recalc_rate(). numerator is defined as u64 whileparent_rate is defined as unsigned long and ctrl_table.fbdivis defined as unsigned int. On 32-bit machine, the result ofthe calculation will be limited to "u32" without correct casting.Integer overflow may occur on high-performance systems.Fixes: 48cf7e01386e ("clk: sophgo: Add SG2042 clock driver")Signed-off-by: Zichen Xie <zichenxie0106@gmail.com>Reviewed-by: Chen Wang <unicorn_wang@outlook.com>Link: https://lore.kernel.org/r/20241023145146.13130-1-zichenxie0106@gmail.comReviewed-by: Dan Carpenter <dan.carpenter@linaro.org>Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: sophgo: clk-sg2042-pll: Fix uninitialized variable in debug outputIf sg2042_get_pll_ctl_setting() fails then "value" isn't initialized andit is printed in the debug output. Initialize it to
clk: sophgo: clk-sg2042-pll: Fix uninitialized variable in debug outputIf sg2042_get_pll_ctl_setting() fails then "value" isn't initialized andit is printed in the debug output. Initialize it to zero.Fixes: 48cf7e01386e ("clk: sophgo: Add SG2042 clock driver")Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>Link: https://lore.kernel.org/r/baf0a490-d5ba-4528-90ba-80399684692d@stanley.mountainReviewed-by: Chen Wang <unicorn_wang@outlook.com>Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Merge branches 'clk-qcom', 'clk-rockchip', 'clk-sophgo' and 'clk-thead' into clk-next - Add support for the AP sub-system clock controller in the T-Head TH1520* clk-qcom: (71 commits) clk: qcom
Merge branches 'clk-qcom', 'clk-rockchip', 'clk-sophgo' and 'clk-thead' into clk-next - Add support for the AP sub-system clock controller in the T-Head TH1520* clk-qcom: (71 commits) clk: qcom: Park shared RCGs upon registration clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks clk: qcom: common: Add interconnect clocks support interconnect: icc-clk: Add devm_icc_clk_register interconnect: icc-clk: Specify master/slave ids dt-bindings: clock: qcom: Add AHB clock for SM8150 clk: qcom: gcc-x1e80100: Set parent rate for USB3 sec and tert PHY pipe clks dt-bindings: interconnect: Add Qualcomm IPQ9574 support clk: qcom: kpss-xcc: Return of_clk_add_hw_provider to transfer the error clk: qcom: lpasscc-sc8280xp: Constify struct regmap_config clk: qcom: gcc-x1e80100: Fix halt_check for all pipe clocks clk: qcom: gcc-ipq6018: update sdcc max clock frequency clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driver dt-bindings: clock: qcom: Add SM8650 camera clock controller dt-bindings: clock: qcom: Update the order of SC8280XP camcc header clk: qcom: videocc-sm8550: Add SM8650 video clock controller clk: qcom: videocc-sm8550: Add support for videocc XO clk ares dt-bindings: clock: qcom: Add SM8650 video clock controller dt-bindings: clock: qcom: Update SM8450 videocc header file name clk: qcom: gpucc-sa8775p: Update wait_val fields for GPU GDSC's ...* clk-rockchip: dt-bindings: clock: rk3188-cru-common: remove CLK_NR_CLKS clk: rockchip: rk3188: Drop CLK_NR_CLKS usage clk: rockchip: Switch to use kmemdup_array() clk: rockchip: rk3128: Add HCLK_SFC dt-bindings: clock: rk3128: Add HCLK_SFC dt-bindings: clock: rk3128: Drop CLK_NR_CLKS clk: rockchip: rk3128: Drop CLK_NR_CLKS usage clk: rockchip: rk3128: Add hclk_vio_h2p to critical clocks clk: rockchip: rk3128: Export PCLK_MIPIPHY dt-bindings: clock: rk3128: Add PCLK_MIPIPHY* clk-sophgo: clk: sophgo: Avoid -Wsometimes-uninitialized in sg2042_clk_pll_set_rate() clk/sophgo: Using BUG() instead of unreachable() in mmux_get_parent_id() clk: sophgo: Add SG2042 clock driver dt-bindings: clock: sophgo: add clkgen for SG2042 dt-bindings: clock: sophgo: add RP gate clocks for SG2042 dt-bindings: clock: sophgo: add pll clocks for SG2042* clk-thead: clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks dt-bindings: clock: Document T-Head TH1520 AP_SUBSYS controller
clk: sophgo: Avoid -Wsometimes-uninitialized in sg2042_clk_pll_set_rate()Clang warns (or errors with CONFIG_WERROR=y): drivers/clk/sophgo/clk-sg2042-pll.c:396:6: error: variable 'ret' is used un
clk: sophgo: Avoid -Wsometimes-uninitialized in sg2042_clk_pll_set_rate()Clang warns (or errors with CONFIG_WERROR=y): drivers/clk/sophgo/clk-sg2042-pll.c:396:6: error: variable 'ret' is used uninitialized whenever 'if' condition is true [-Werror,-Wsometimes-uninitialized] 396 | if (sg2042_pll_enable(pll, 0)) { | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/sophgo/clk-sg2042-pll.c:418:9: note: uninitialized use occurs here 418 | return ret; | ^~~ drivers/clk/sophgo/clk-sg2042-pll.c:396:2: note: remove the 'if' if its condition is always false 396 | if (sg2042_pll_enable(pll, 0)) { | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 397 | pr_warn("Can't disable pll(%s), status error\n", pll->hw.init->name); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 398 | goto out; | ~~~~~~~~~ 399 | } | ~ drivers/clk/sophgo/clk-sg2042-pll.c:393:9: note: initialize the variable 'ret' to silence this warning 393 | int ret; | ^ | = 0 1 error generated.sg2042_pll_enable() only ever returns zero, so this situation cannothappen, but clang does not perform interprocedural analysis, so itcannot know this to avoid the warning. Make it clearer to the compilerby making sg2042_pll_enable() void and eliminate the error handling insg2042_clk_pll_set_rate(), which clears up the warning, as ret willalways be initialized.Fixes: 48cf7e01386e ("clk: sophgo: Add SG2042 clock driver")Signed-off-by: Nathan Chancellor <nathan@kernel.org>Link: https://lore.kernel.org/r/20240710-clk-sg2042-fix-sometimes-uninitialized-pll_set_rate-v1-1-538fa82dd539@kernel.orgSigned-off-by: Stephen Boyd <sboyd@kernel.org>
clk/sophgo: Using BUG() instead of unreachable() in mmux_get_parent_id()In general it's a good idea to avoid using bare unreachable() because itintroduces undefined behavior in compiled code. but
clk/sophgo: Using BUG() instead of unreachable() in mmux_get_parent_id()In general it's a good idea to avoid using bare unreachable() because itintroduces undefined behavior in compiled code. but it caused a compilation warning,Using BUG() instead of unreachable() to resolve compilation warnings.Fixes the following warnings: drivers/clk/sophgo/clk-cv18xx-ip.o: warning: objtool: mmux_round_rate() falls through to next function bypass_div_round_rate()Fixes: 80fd61ec46124 ("clk: sophgo: Add clock support for CV1800 SoC")Signed-off-by: Li Qiang <liqiang01@kylinos.cn>Link: https://lore.kernel.org/r/c8e66d51f880127549e2a3e623be6787f62b310d.1720506143.git.liqiang01@kylinos.cnSigned-off-by: Stephen Boyd <sboyd@kernel.org>
clk: sophgo: Add SG2042 clock driverAdd a driver for the SOPHGO SG2042 clocks.Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
clk: sophgo: add missing MODULE_DESCRIPTION() macromake allmodconfig && make W=1 C=1 reports:WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sophgo/clk-sophgo-cv1800.oAdd the missi
clk: sophgo: add missing MODULE_DESCRIPTION() macromake allmodconfig && make W=1 C=1 reports:WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sophgo/clk-sophgo-cv1800.oAdd the missing invocation of the MODULE_DESCRIPTION() macro.Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com>Link: https://lore.kernel.org/r/20240601-md-drivers-clk-sophgo-clk-sophgo-cv1800-v1-1-8e00d8c3a87b@quicinc.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
clk: sophgo: avoid open-coded 64-bit divisionOn 32-bit architectures, the 64-bit division leads to a link failure:arm-linux-gnueabi-ld: drivers/clk/sophgo/clk-cv18xx-pll.o: in function `fpll_calc
clk: sophgo: avoid open-coded 64-bit divisionOn 32-bit architectures, the 64-bit division leads to a link failure:arm-linux-gnueabi-ld: drivers/clk/sophgo/clk-cv18xx-pll.o: in function `fpll_calc_rate':clk-cv18xx-pll.c:(.text.fpll_calc_rate+0x26): undefined reference to `__aeabi_uldivmod'This one is not called in a fast path, and there is already another div_u64()variant used in the same function, so convert it to div64_u64_rem().Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC")Signed-off-by: Arnd Bergmann <arnd@arndb.de>Link: https://lore.kernel.org/r/20240415134532.3467817-1-arnd@kernel.orgReported-by: kernel test robot <lkp@intel.com>Closes: https://lore.kernel.org/oe-kbuild-all/202404122344.d5pb2N1I-lkp@intel.com/Closes: https://lore.kernel.org/oe-kbuild-all/202404140310.QEjZKtTN-lkp@intel.com/Reviewed-by: Inochi Amaoto <inochiama@outlook.com>Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: sophgo: Make synthesizer struct staticLet all synthesizer structs are static to make the compiler happy.Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC")Signed-off-by: I
clk: sophgo: Make synthesizer struct staticLet all synthesizer structs are static to make the compiler happy.Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC")Signed-off-by: Inochi Amaoto <inochiama@outlook.com>Link: https://lore.kernel.org/r/IA1PR20MB49531E437735A71A163694AEBB052@IA1PR20MB4953.namprd20.prod.outlook.comReported-by: kernel test robot <lkp@intel.com>Closes: https://lore.kernel.org/oe-kbuild-all/202404120548.y9dZIi0e-lkp@intel.com/Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: sophgo: Add clock support for SG2000 SoCAdd init code for SG2000 SoC.Signed-off-by: Inochi Amaoto <inochiama@outlook.com>Link: https://github.com/sophgo/sophgo-doc/releases/tag/sg2000-datas
clk: sophgo: Add clock support for SG2000 SoCAdd init code for SG2000 SoC.Signed-off-by: Inochi Amaoto <inochiama@outlook.com>Link: https://github.com/sophgo/sophgo-doc/releases/tag/sg2000-datasheet-v1.0-alphaLink: https://lore.kernel.org/r/IA1PR20MB49537156E71B64483F15C0F2BB262@IA1PR20MB4953.namprd20.prod.outlook.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
clk: sophgo: Add clock support for CV1810 SoCAdd clock definition and init code for CV1810 SoC.Signed-off-by: Inochi Amaoto <inochiama@outlook.com>Link: https://github.com/milkv-duo/duo-files/bl
clk: sophgo: Add clock support for CV1810 SoCAdd clock definition and init code for CV1810 SoC.Signed-off-by: Inochi Amaoto <inochiama@outlook.com>Link: https://github.com/milkv-duo/duo-files/blob/6f4e9b8ecb459e017cca1a8df248a19ca70837a3/duo/datasheet/CV180X-Clock-v1.xlsxLink: https://lore.kernel.org/r/IA1PR20MB495357FB5EEA1623DAB08C94BB262@IA1PR20MB4953.namprd20.prod.outlook.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
clk: sophgo: Add clock support for CV1800 SoCAdd clock definition and driver code for CV1800 SoC.Signed-off-by: Inochi Amaoto <inochiama@outlook.com>Link: https://github.com/milkv-duo/duo-files/
clk: sophgo: Add clock support for CV1800 SoCAdd clock definition and driver code for CV1800 SoC.Signed-off-by: Inochi Amaoto <inochiama@outlook.com>Link: https://github.com/milkv-duo/duo-files/blob/6f4e9b8ecb459e017cca1a8df248a19ca70837a3/duo/datasheet/CV180X-Clock-v1.xlsxLink: https://github.com/milkv-duo/duo-files/blob/6f4e9b8ecb459e017cca1a8df248a19ca70837a3/duo/datasheet/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdfLink: https://lore.kernel.org/r/IA1PR20MB49534F37F802CAF117364D66BB262@IA1PR20MB4953.namprd20.prod.outlook.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>