| 0528a348 | 30-Jan-2026 |
Felix Gu <ustc.gu@gmail.com> |
cache: ax45mp: Fix device node reference leak in ax45mp_cache_init()
In ax45mp_cache_init(), of_find_matching_node() returns a device node with an incremented reference count that must be released w
cache: ax45mp: Fix device node reference leak in ax45mp_cache_init()
In ax45mp_cache_init(), of_find_matching_node() returns a device node with an incremented reference count that must be released with of_node_put(). The current code fails to call of_node_put() which causes a reference leak.
Use the __free(device_node) attribute to ensure automatic cleanup when the variable goes out of scope.
Fixes: d34599bcd2e4 ("cache: Add L2 cache management for Andes AX45MP RISC-V core") Signed-off-by: Felix Gu <ustc.gu@gmail.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 2ec3b54a | 17-Nov-2025 |
Yushan Wang <wangyushan12@huawei.com> |
cache: Support cache maintenance for HiSilicon SoC Hydra Home Agent
Hydra Home Agent is a device used to maintain cache coherency. Add support for explicit cache maintenance operations using it. A s
cache: Support cache maintenance for HiSilicon SoC Hydra Home Agent
Hydra Home Agent is a device used to maintain cache coherency. Add support for explicit cache maintenance operations using it. A system has multiple of these agents. Whilst only one agent is responsible for a given cache line, interleave means that for a range operation, responsibility for the cache lines making up the range will typically be spread across multiple instances.
Put this driver on a new Kconfig menu under drivers/cache. The short description as memory hotplug like operations is intended to cover the somewhat complex set of cases where this unit applies and differentiate it clearly from typical non coherent DMA flows.
Co-developed-by: Yicong Yang <yangyicong@hisilicon.com> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Signed-off-by: Yushan Wang <wangyushan12@huawei.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 4d1608d0 | 17-Nov-2025 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> |
cache: Make top level Kconfig menu a boolean dependent on RISCV
The next patch will add a new type of cache maintenance driver responsible for flushing deeper than is necessary for non coherent DMA
cache: Make top level Kconfig menu a boolean dependent on RISCV
The next patch will add a new type of cache maintenance driver responsible for flushing deeper than is necessary for non coherent DMA (current use case of drivers/cache drivers), as needed when performing operations such as memory hotplug and security unlocking of persistent memory. The two types of operation are similar enough to share a drivers/cache directory and MAINTAINERS but are otherwise currently unrelated.
To avoid confusion have two separate menus. Each has dependencies that are implemented by making them boolean symbols, here CACHEMAINT_FOR_DMA which is dependent on RISCV as all driver are currently for platforms of that architecture. Set new symbol default to y to avoid breaking existing configs. This has no affect on actual code built, just visibility of the menu.
Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 6b0856ee | 11-Apr-2024 |
Samuel Holland <samuel.holland@sifive.com> |
cache: sifive_ccache: Silence unused variable warning
With W=1 and CONFIG_RISCV_NONSTANDARD_CACHE_OPS=n, GCC warns:
drivers/cache/sifive_ccache.c: In function 'sifive_ccache_init': drivers/cache/si
cache: sifive_ccache: Silence unused variable warning
With W=1 and CONFIG_RISCV_NONSTANDARD_CACHE_OPS=n, GCC warns:
drivers/cache/sifive_ccache.c: In function 'sifive_ccache_init': drivers/cache/sifive_ccache.c:293:23: warning: variable 'quirks' set but not used [-Wunused-but-set-variable] 293 | unsigned long quirks; | ^~~~~~
This is expected, since QUIRK_NONSTANDARD_CACHE_OPS is the only quirk still handled in this function.
Fixes: c90847bcbfb6 ("cache: sifive_ccache: Partially convert to a platform driver") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202403311253.Z4NvIBxI-lkp@intel.com/ Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 0d5701dc | 31-Oct-2023 |
Emil Renner Berthing <kernel@esmil.dk> |
soc: sifive: ccache: Add StarFive JH7100 support
This adds support for the StarFive JH7100 SoC which also features this SiFive cache controller.
The JH7100 has non-coherent DMAs but predate the sta
soc: sifive: ccache: Add StarFive JH7100 support
This adds support for the StarFive JH7100 SoC which also features this SiFive cache controller.
The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom exension, so instead we need to use this cache controller for non-standard cache management operations.
Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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