Merge tag 'riscv-for-linus-7.3-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V updates from Paul Walmsley

- Add initial definitions and discovery for the Smcsrind, Ss

Merge tag 'riscv-for-linus-7.3-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V updates from Paul Walmsley

- Add initial definitions and discovery for the Smcsrind, Sscsrind,
Smcntrpmf, Ssccfg, Smcdeleg, Zicclsm, Ziccamoa, Ziccif, Ziccrse,
Za64rs, and Ssqosid RISC-V ISA extensions

- Improve the RISC-V update_mmu_cache_range() implementation by using
flush-by-ASID, enabling performance improvements on
microarchitectures that support related optimizations; and by taking
advantage of the Svinval RISC-V ISA extension on microarchitectures
that support it

- Shrink CFI shadow stack allocation further (to 512MB) to save virtual
address space (and physical memory on systems with strict overcommit
policies)

- Add initial CPU context switch support for QoS tagging (Ssqosid)

- Change our vector misaligned access speed test code to be
synchronous, avoiding a bunch of bugs related to unnecessary
asynchronicity

- Enable ARCH_HAS_ACPI_TABLE_UPGRADE for RISC-V to help with ACPI table
debugging (similar to ARM64 and x86)

- Extract vDSO section offsets at build time, rather than run time, to
avoid the boot time overhead

- Use assembler directives to control the use of instructions from the
RISC-V ISA extensions Zacas and Zabha, rather than compiler -march
flags that could affect the whole kernel (similar to ARM64)

- Add a kselftest for kprobes support for the c.jal instruction on
RISC-V

- When UEFI runtime services are available, use them to restart and
power off

- Fix ARCH_HAS_ACPI_TABLE_UPGRADE for RISC-V by adding a missing
include file to the ACPI code

- Move contiguous DMA memory reservation later in the boot, to ensure
that the correct global and per-node pools are allocated when
CONFIG_CMA_SIZE_PERNUMA is enabled

- Disallow probes on breakpoint handlers to avoid recursing
indefinitely into do_trap_break()

- Patch the compat vDSO during runtime alternatives processing, not
only the standard vDSO

- Remove some leftover XIP support elements missed by commit
9b3a2be84803 ("riscv: Remove support for XIP kernel")

- Fix broadcast timer switching in ACPI LPI power states by
implementing a RISC-V version of arch_get_idle_state_flags()

- Miscellaneous fixes, including: vDSO makefile simplification; marking
our default_power_off() as __noreturn; error path fixes in the PMU
SBI perf driver; RISC-V extension capitalization consistency; the use
of BIT() macros in one of our include files; and some documentation
fixes

* tag 'riscv-for-linus-7.3-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (39 commits)
RISC-V: hwprobe: Use BIT macro to avoid warnings
riscv: alternative: Also patch the compat vDSO
riscv: alternative: Use the statically extracted vDSO section offsets
riscv: vdso: Add symbols for the alternative section boundaries
riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to cpufeature and hwprobe
riscv: Add Zicclsm to cpufeature and hwprobe
riscv: cpufeature: Clarify ISA spec version for canonical order
riscv: Standardize extension capitalization
riscv: kprobes: Prevent probes in breakpoint handlers
riscv: cmpxchg: Use .option arch for Zacas and Zabha
riscv: acpi: Handle LPI architectural context loss flags
riscv: further remove XIP
riscv: Add support for srmcfg CSR from Ssqosid extension
riscv: Detect the Ssqosid extension
dt-bindings: riscv: Add Ssqosid extension description
dt-bindings: riscv: add Counter delegation ISA extensions description
RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing
RISC-V: Add Ssccfg extension CSR definition
dt-bindings: riscv: add Smcntrpmf ISA extension description
RISC-V: Add Smcntrpmf extension parsing
...

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riscv: Add support for srmcfg CSR from Ssqosid extension

Add support for the srmcfg CSR defined in the Ssqosid ISA extension.
The CSR contains two fields:

- Resource Control ID (RCID) for resourc

riscv: Add support for srmcfg CSR from Ssqosid extension

Add support for the srmcfg CSR defined in the Ssqosid ISA extension.
The CSR contains two fields:

- Resource Control ID (RCID) for resource allocation
- Monitoring Counter ID (MCID) for tracking resource usage

Requests from a hart to shared resources are tagged with these IDs,
allowing resource usage to be associated with the running task.

Add a srmcfg field to thread_struct with the same format as the CSR.
The context-switch path writes the field to the CSR, and
resctrl_arch_set_closid_rmid() updates it when a task is assigned to a
resctrl control or monitoring group.

A per-cpu cpu_srmcfg_default holds the default srmcfg for each CPU, set
by resctrl_arch_set_cpu_default_closid_rmid() on CPU group assignment.
On context switch, RCID and MCID inherit from the CPU default
independently: a task whose thread RCID field is zero takes the CPU
default's RCID, and likewise for MCID.

A per-cpu cpu_srmcfg variable mirrors the CSR state to avoid
redundant writes. L1D-hot memory access is faster than a CSR read and
avoids traps under virtualization.

Link: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0
Assisted-by: Claude:claude-opus-4-7
Co-developed-by: Kornel Dulęba <mindal@semihalf.com>
Signed-off-by: Kornel Dulęba <mindal@semihalf.com>
Signed-off-by: Drew Fustini <fustini@kernel.org>
Link: https://patch.msgid.link/20260729-dfustini-atl-sc-cbqri-dt-v6-3-7c22b05d461b@kernel.org
Signed-off-by: Paul Walmsley <pjw@kernel.org>

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