riscv: errata: Fix bitwise vs logical AND in MIPS errata patchingThe condition checking whether a specific errata needs patching useslogical AND (&&) instead of bitwise AND (&). Since logical AND
riscv: errata: Fix bitwise vs logical AND in MIPS errata patchingThe condition checking whether a specific errata needs patching useslogical AND (&&) instead of bitwise AND (&). Since logical AND onlychecks that both operands are non-zero, this causes all errata patchesto be applied whenever any single errata is detected, rather than onlyapplying the matching one.The SiFive errata implementation correctly uses bitwise AND for the samecheck.Fixes: 0b0ca959d206 ("riscv: errata: Fix the PAUSE Opcode for MIPS P8700")Signed-off-by: Michael Neuling <mikey@neuling.org>Assisted-by: Cursor:claude-4.6-opus-high-thinkingLink: https://patch.msgid.link/20260409091143.1348853-2-mikey@neuling.org[pjw@kernel.org: fixed checkpatch warning]Signed-off-by: Paul Walmsley <pjw@kernel.org>
show more ...
riscv: errata: Fix the PAUSE Opcode for MIPS P8700Add ERRATA_MIPS and ERRATA_MIPS_P8700_PAUSE_OPCODE configs.Handle errata for the MIPS PAUSE instruction.Signed-off-by: Djordje Todorovic <djordj
riscv: errata: Fix the PAUSE Opcode for MIPS P8700Add ERRATA_MIPS and ERRATA_MIPS_P8700_PAUSE_OPCODE configs.Handle errata for the MIPS PAUSE instruction.Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>Signed-off-by: Aleksandar Rikalo <arikalo@gmail.com>Signed-off-by: Raj Vishwanathan4 <rvishwanathan@mips.com>Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>Link: https://lore.kernel.org/r/20250724-p8700-pause-v5-7-a6cbbe1c3412@htecgroup.com[pjw@kernel.org: updated to apply and compile; fixed a checkpatch issue]Signed-off-by: Paul Walmsley <pjw@kernel.org>