| 04b153ab | 19-Jun-2023 |
Sergio Paracuellos <sergio.paracuellos@gmail.com> |
mips: ralink: mt7620: remove clock related code
A proper clock driver for ralink SoCs has been added. Hence there is no need to have clock related code in 'arch/mips/ralink' folder anymore. Since th
mips: ralink: mt7620: remove clock related code
A proper clock driver for ralink SoCs has been added. Hence there is no need to have clock related code in 'arch/mips/ralink' folder anymore. Since this is the last clock related code removal, remove also remaining prototypes in 'common.h' header file.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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| 7cd1bb48 | 19-Jun-2023 |
Sergio Paracuellos <sergio.paracuellos@gmail.com> |
mips: ralink: rt3883: remove clock related code
A properly clock driver for ralink SoCs has been added. Hence there is no need to have clock related code in 'arch/mips/ralink' folder anymore.
Signe
mips: ralink: rt3883: remove clock related code
A properly clock driver for ralink SoCs has been added. Hence there is no need to have clock related code in 'arch/mips/ralink' folder anymore.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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| daf73c70 | 19-Jun-2023 |
Sergio Paracuellos <sergio.paracuellos@gmail.com> |
mips: ralink: rt305x: remove clock related code
A properly clock driver for ralink SoCs has been added. Hence there is no need to have clock related code in 'arch/mips/ralink' folder anymore.
Signe
mips: ralink: rt305x: remove clock related code
A properly clock driver for ralink SoCs has been added. Hence there is no need to have clock related code in 'arch/mips/ralink' folder anymore.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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| ebe7e788 | 25-Sep-2021 |
Sergio Paracuellos <sergio.paracuellos@gmail.com> |
MIPS: ralink: set PCI_IOBASE to 'mips_io_port_base'
By default MIPS architecture use function 'set_io_port_base()' to set the virtual address of the first IO port. This function at the end sets vari
MIPS: ralink: set PCI_IOBASE to 'mips_io_port_base'
By default MIPS architecture use function 'set_io_port_base()' to set the virtual address of the first IO port. This function at the end sets variable 'mips_io_port_base' with the desired address. To align things and allow to change first IO port location address for PCI, set PCI_IOBASE definition as 'mips_io_port_base'.
Fixes: 222b27713d7f ("MIPS: ralink: Define PCI_IOBASE") Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210925203224.10419-4-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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