Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 updates from Catalin Marinas:
"Here are the arm64 updates for 7.4.

The more interesting bits ar

Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 updates from Catalin Marinas:
"Here are the arm64 updates for 7.4.

The more interesting bits are the removal of big-endian kernel support
(already marked BROKEN for some time), preemptible this_cpu_*()
operations and MPAM support for the firmware-backed (Fb) interface.

CCA (Arm's confidential compute) is slowly trickling in with host RMI
(Realm Management Interface) support and some refactoring, including a
dedicated SMCCC bus to advertise firmware services. There are also the
usual PMU updates for new hardware and a few fixes/cleanups.

Core features:

- Remove big-endian kernel support: CONFIG_CPU_BIG_ENDIAN has
depended on BROKEN for a while, so drop the remaining code (BE
hypervisor object, BPF JIT, assembly/crypto/library routines,
endianness helper macros, selftests) and force a little-endian
build

- Add preemptible this_cpu_*() operations (read/write, RMW, xchg,
cmpxchg and cmpxchg128) that no longer need to disable preemption
around the per-CPU address generation and access

- Preparation patches for implementing CONFIG_HOTPLUG_PARALLEL on
arm64

Memory management:

- Treat faults taken by EFI runtime firmware as kernel faults

- Clear PTE_WRITE for EFI_MEMORY_RO mappings (with hardware dirty
state management enabled, this is not truly read-only)

- Raise the default ARCH_MMAP_RND_BITS for 48-bit and 52-bit VA
configurations (28/26/24 bits for 4K/16K/64K pages)

- Implement clear_page[s]() using memset()

- Enable BBML2 no-abort (a.k.a. BBML3) for the NVIDIA Rigel CPU

Perf and PMU:

- Support for HiSilicon's ITS PMU

- Add support for some new events: INST_SIMD_ALU_VEC for Apple PMUs
and a cycle counter for the latest version of HiSilicon's MN PMU
hardware

- A bunch of fixes to the CXL PMU driver to address pre-existing
issues from Sashiko

- Fix generation of PERF_RECORD_ITRACE_START records for SPE and ETM
drivers

- Reduce excessive stack consumption in the Marvell DDR PMU driver

- Minor driver updates and cleanups all over

Arm Confidential Compute Architecture (CCA):

- Add an Arm SMCCC bus for firmware services discovered through SMCCC
and move the TRNG and CCA guest (TSM provider) drivers onto it,
removing the dummy CCA platform device and adding a sysfs ABI for
Realm guests

- Move the Realm Service Interface (RSI) code out of arch/arm64/ into
drivers/firmware/arm_rmm/

- Add the host side of the Realm Management Interface (RMI): detect,
configure and activate the RMM, add SRO support and wrappers for
the Realm RMI commands

- Block hibernation (new arch hook in the PM core) and kexec while
the RMM is active. To be revisited in the future with proper
support for deactivation

- Handle Granule Protection Faults (GPFs) taken by the host, caused
by accesses to memory delegated to the RMM. In a future patch, the
exception table lookup will be limited to is_kdump_kernel() cases

MPAM (Memory Partitioning And Monitoring):

- Add support for the MPAM firmware-backed (Fb) interface, allowing
MSC accesses to be mediated by firmware

- Fix a list of theoretical issues with the driver (MSC access error
propagation, MBWU monitor save/restore and locking, resctrl class
handling, error interrupt restore, maximum number of PARTIDs)

- Add the mailing list and a missing file to the MAINTAINERS entry

- Document when to set arm64.nompam

Errata and CPU features:

- Add the NXP i.MX8QM/8QP workaround for the Cortex-A53 cache
coherency issue (ERR050104), using a new ARM64_CPUCAP_SOC_ERRATUM
capability type for SoC-level errata

Miscellaneous:

- Mask debug exceptions (DAIF) around the hardware breakpoint
register manipulations when called from generic kernel code

- Don't zero the SVE state buffer when the SVE state is live

- Return -EPERM instead of -EBUSY from the GCS prctl() locking
failures (matching x86), with the selftest updated. Slight ABI
change but no software deployment yet

- kselftest: fix unsound MTE fault skipping by introducing MTE-safe
memory accessors, avoid copying each signal test binary more than
once

- Update sysreg definitions (fix three enum values and two field
names, mark architecturally dropped fields as RES0) and remove the
TME transaction state check from the BRBE driver

- Fix the description of ARM64_HAS_LPA2 and remove a redundant
ID_AA64MMFR0 define"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (144 commits)
arm64: cpufeature: Enable BBML2 for NVIDIA Rigel
arm64: cputype: Add NVIDIA Rigel definitions
arm64: raise default ARCH_MMAP_RND_BITS for 48-bit and 52-bit VA
arm64/debug: mask debug exceptions when called from common code
kselftest/arm64: signal: copy each test binary only once
kselftest/arm64: Check for -EPERM not -EBUSY in the locking test
arm64: gcs: Return -EPERM not -EBUSY for prctl() locking failures
perf: arm_brbe: Remove the check for TME transaction states
arm64: sysreg: Mark fields the architecture dropped as RES0
arm64: sysreg: Fix the names of two misspelt fields
arm64: sysreg: Fix three incorrect enum values
arm64: smp: Defer RCU registration during secondary CPU bringup
arm64: smp: Don't bother printing the I-cache policy for each CPU
arm64: smp: Defer update of secondary CPU capabilities
arm64: smp: Tidy up cpuinfo init and cpufeature updates
arm64: smp: Tidy up smp_prepare_cpus()
arm64: cpufeature: Store every ID register with its overrides applied
arm64: cpufeature: Read MPAMIDR_EL1 in __cpuinfo_store_cpu()
arm64: cpufeature: Add read_cpuid_with_overrides()
arm64: cpufeature: Check arm64_ftr_regs[] before the first store
...

show more ...

Merge branches 'for-next/misc', 'for-next/be-gone', 'for-next/smccc-bus', 'for-next/preemptible-this-cpu', 'for-next/cpu-errata', 'for-next/mpam', 'for-next/kselftest', 'for-next/efi', 'for-next/seco

Merge branches 'for-next/misc', 'for-next/be-gone', 'for-next/smccc-bus', 'for-next/preemptible-this-cpu', 'for-next/cpu-errata', 'for-next/mpam', 'for-next/kselftest', 'for-next/efi', 'for-next/secondary-boot-prep', 'for-next/sysreg' and 'for-next/gcs', remote-tracking branch 'arm64/for-next/perf' into for-next/core

* arm64/for-next/perf: (22 commits)
drivers/perf: apple_m1: Add macOS 27 M2 Event
perf/marvell: cn10k_tad: Publish the OF module alias
perf: xgene: initialize lock before requesting IRQ
perf: marvell: avoid large stack variables
perf/dwc_pcie: Fix PCI device reference leak in probe
coresight: perf: Suppress ITRACE start records
perf: arm_spe: Suppress redundant ITRACE start records
perf/core: Export perf_event_itrace_started()
perf/cxl: Clear stale overflow status before using a counter
perf/cxl: Don't log through pmu.dev in the overflow interrupt handler
perf/cxl: Validate the hardware-reported counter width
perf/cxl: Unfreeze counters after handling an overflow interrupt
perf/cxl: Don't share the overflow interrupt, and keep it pinned
cxl/pci: Add the PMUs after configuring events
perf/cxl: Split the MSI vector out of info->irq
perf/cxl: Accept an overflow interrupt on MSI message number 0
perf/cxl: Fix the counter overflow delta fixup
perf/cxl: Clear stale event fields before reprogramming a counter
perf/cxl: Program the requested event group on configurable counters
drivers/perf: hisi: Add cycle event for new MN PMU
...

* for-next/misc:
arm64: cpufeature: Enable BBML2 for NVIDIA Rigel
arm64: cputype: Add NVIDIA Rigel definitions
arm64: raise default ARCH_MMAP_RND_BITS for 48-bit and 52-bit VA
arm64/debug: mask debug exceptions when called from common code
arm64: clear_page[s] using memset
arm64/sve: Don't zero the SVE state buffer when the SVE state is live
arm64/cpufeature: Drop redundant define(ID_AA64MMFR0..._SUPPORTED_LPA2)
arm64: Use proper include variant
arm64: include: fix repeated word 'to' in comment
selftests: arm64: fix typo "hander" in comment
arm64: fix typos in comments
docs: arm64: Fix typo "initalised" in booting.rst
arm64: alternative: Remove 'cfg' parameter
arm64: mte-kasan: Use IS_ENABLED() rather than ALTERNATIVE() 'cfg' parameter
arm64/cpufeature: Change description for ARM64_HAS_LPA2

* for-next/be-gone:
drivers: Kconfig: Simplify dependencies on ARM64 && !CPU_BIG_ENDIAN
arm64: Kbuild: Remove vestigial big-endian support
gve: Add explicit ARM64 dependency to Kconfig
crypto: hisilicon/sec2: Remove check of CONFIG_CPU_LITTLE_ENDIAN
arm64: Remove all usage of __AARCH64EB__
arm64: Remove all usage of CONFIG_CPU_BIG_ENDIAN
KVM: arm64: Remove support for a big-endian hypervisor object
arm64: vdso32: Always build compat vDSO object as little-endian
arm64: assembler: Remove endianness helper macros
arm64: lib: Assume a little-endian kernel in optimised string routines
arm64: lib: Assume a little-endian kernel in custom library routines
arm64: crypto: Assume a little-endian kernel
arm64: bpf: Remove big-endian support from the JIT compiler
selftests/arm64: Remove big-endian support

* for-next/smccc-bus:
: Switch Arm SMCCC firmware services to an SMCCC bus
arm64: rsi: Correct type of realm_config::hash_algo
firmware: smccc: Pass only the required device probe arguments
firmware: arm_rmm: Add SPDX and sort the Kconfig and Makefile entries
coco: guest: arm64: Remove dummy CCA platform device
coco: guest: arm64: Add sysfs ABI for CCA Realm guests
firmware: smccc: arm-cca-guest: Bind the TSM provider to an SMCCC device
virt: coco: arm-cca-guest: Rename TSM report source file
arm64: realm: Move Realm memory encryption ops to RSI code
firmware: arm_rmm: Move RSI support out of arch/arm64
firmware: hwrng: arm_smccc_trng: Register as an SMCCC device
firmware: smccc: Add an Arm SMCCC bus

* for-next/preemptible-this-cpu:
: Preemptible this_cpu_*() operations
arm64: percpu: Remove _pcp_protect*() wrappers
arm64: percpu: Implement preemptible CMPXCHG128 ops
arm64: percpu: Implement preemptible CMPXCHG ops
arm64: percpu: Implement preemptible XCHG ops
arm64: percpu: Implement preemptible return RMW ops
arm64: percpu: Implement preemptible void RMW ops
arm64: percpu: Implement preemptible read/write ops
arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops
arm64: entry: sdei: Make 'tsk' available
arm64: entry: sdei: Restore all clobberable GPRs
arm64: gpr-num: add __GPR_NUM() helper
arm64: gpr-num: Add wxN aliases for wN registers
arm64: percpu: Factor out percpu offset asm
arm64: ptrace: Always inline pt_regs_{read,write}_reg()
arm64: preempt: Treat should_resched() as unlikely
arm64: preempt: Simplify and optimize __preempt_count_dec_and_test()
arm64: cmpxchg128: LSE: Remove redundant operands
arm64: cmpxchg: LL/SC: Avoid redundant extension

* for-next/cpu-errata:
: Various CPU errata workarounds
arm64: errata: Add NXP i.MX8QM/8QP workaround for A53 cache coherency issue
arm64: cpufeature: Add ARM64_CPUCAP_SOC_ERRATUM for SoC-level errata

* for-next/mpam: (30 commits)
: MPAM updates
arm_mpam: make the mon_sel guard conditional only
arm_mpam: On saving mbwu state read the monitors before clearing CFG_MBWU_CTL
arm_mpam: detect and enable MPAM-Fb PCC support
arm_mpam: change MPAM-Fb error IRQ to use a threaded IRQ handler
arm_mpam: add MPAM-Fb MSC firmware access support
arm_mpam: prepare mon_sel locking for MPAM-Fb
arm_mpam: propagate MSC access errors in mpam_reset_class_locked()
arm_mpam: propagate MSC access errors for interrupt control
arm_mpam: propagate MSC access errors for mpam_reprogram_ris_partid()
arm_mpam: propagate MSC access errors for state saving function
arm_mpam: propagate MSC access errors for __ris_msmon_read()
arm_mpam: propagate MSC access errors for msmon helpers
arm_mpam: propagate MSC access errors for MBWU counters
arm_mpam: propagate MSC access errors for hw_probe functions
arm_mpam: let low level MSC accessors return an error
MAINTAINERS: Use linux-arm-kernel list for the MPAM driver
MAINTAINERS: Add mpam.rst to the MPAM DRIVER entry
arm_mpam: resctrl: Don't stop early when tearing down a class
arm_mpam: Switch to kvzmalloc_objs() for allocation of component cfg
arm_mpam: Don't loop forever if there is the maximum possible amount of PARTIDs
...

* for-next/kselftest:
: arm64 kselftest updates
kselftest/arm64: signal: copy each test binary only once
kselftest/arm64/mte: Use MTE safe memory accessors
kselftest/arm64/mte: Introduce MTE safe memory accessors
kselftest/arm64: Extend gcs-locking to cover cases where enable is unlocked

* for-next/efi:
: arm64 EFI updates/fixes
arm64/mm: Treat faults taken by EFI runtime firmware as kernel faults
arm64/efi: Clear PTE_WRITE when applying EFI_MEMORY_RO

* for-next/secondary-boot-prep:
: cpuinfo cleanup in preparation for parallel secondary bring-up
arm64: smp: Defer RCU registration during secondary CPU bringup
arm64: smp: Don't bother printing the I-cache policy for each CPU
arm64: smp: Defer update of secondary CPU capabilities
arm64: smp: Tidy up cpuinfo init and cpufeature updates
arm64: smp: Tidy up smp_prepare_cpus()
arm64: cpufeature: Store every ID register with its overrides applied
arm64: cpufeature: Read MPAMIDR_EL1 in __cpuinfo_store_cpu()
arm64: cpufeature: Add read_cpuid_with_overrides()
arm64: cpufeature: Check arm64_ftr_regs[] before the first store

* for-next/sysreg:
: sysreg updates
perf: arm_brbe: Remove the check for TME transaction states
arm64: sysreg: Mark fields the architecture dropped as RES0
arm64: sysreg: Fix the names of two misspelt fields
arm64: sysreg: Fix three incorrect enum values

* for-next/gcs:
: GCS updates/fixes
kselftest/arm64: Check for -EPERM not -EBUSY in the locking test
arm64: gcs: Return -EPERM not -EBUSY for prctl() locking failures

show more ...

arm64: cmpxchg: LL/SC: Avoid redundant extension

The __ll_sc__cmpxchg_case_##name##sz() template always takes 'old' as an
unsigned long. When 'sz' is less than 32 bits, the 'old' is explicitly
trunc

arm64: cmpxchg: LL/SC: Avoid redundant extension

The __ll_sc__cmpxchg_case_##name##sz() template always takes 'old' as an
unsigned long. When 'sz' is less than 32 bits, the 'old' is explicitly
truncated so that old[31:sz-1] is zero, which is necessary so that the
W-register EOR+CBNZ sequence doesn't fail spuriously.

For 32-bit types specifically, no extension is necessary, but as 'old'
is 64 bits, the caller must extend 'old' to 64 bits. This leads to a
redundant instruction (typically a MOV) to extend the value, as can be
seen from disassembly of the test case below.

Avoid this by always taking 'old' as a 'u##sz' type, and explicitly
zero-extend this to a 64-bit or 32-bit type matching the X or W register
used by the assembly. To make this work, the table of cases now
explicitly lists 'x' for the cases where an X register is used.

For 32-bit types this removes the redundant instruction. For 64-bit
types there is no truncation, and hence no change. For {16,8}-bit types,
the existing zero-extension to 64-bit is equivalent to the new
zero-extension to 32-bit, and compilers happen to use the same
instructions for this.

I've placed the logic for zero extension into a new <asm/xwreg.h> header
as it will be used by other logic in subsequent patches.

Test case:

| u32 outline_cmpxchg_u32(u32 *p, u32 o, u32 n)
| {
| return cmpxchg(p, o, n);
| }

Before this patch:

| <outline_cmpxchg_u32>:
| b 1f
| casal w1, w2, [x0]
| mov w0, w1
| ret
| 1: mov w3, w1
| prfm pstl1strm, [x0]
| 2: ldxr w1, [x0]
| eor w4, w1, w3
| cbnz w4, 3f
| stlxr w4, w2, [x0]
| cbnz w4, 2b
| dmb ish
| 3: mov w0, w1
| ret

After this patch:

| <outline_cmpxchg_u32>:
| b 1f
| casal w1, w2, [x0]
| mov w0, w1
| ret
| 1: prfm pstl1strm, [x0]
| 2: ldxr w3, [x0]
| eor w4, w3, w1
| cbnz w4, 3f
| stlxr w4, w2, [x0]
| cbnz w4, 2b
| dmb ish
| 3: mov w0, w3
| ret

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Muhammad Usama Anjum <usama.anjum@arm.com>
Cc: Ada Couprie Diaz <ada.coupriediaz@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Jinjie Ruan <ruanjinjie@huawei.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Vladimir Murzin <vladimir.murzin@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Yang Shi <yang@os.amperecomputing.com>
Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

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