arm64: dts: ti: k3-am62a-wakeup: Configure ti-sysc for wkup_uart0

Similar to the TI K3-AM62x SoC commit ce27f7f9e328c8582a169f97f1466976561f1
("arm64: dts: ti: k3-am62-wakeup: Configure ti-sysc for

arm64: dts: ti: k3-am62a-wakeup: Configure ti-sysc for wkup_uart0

Similar to the TI K3-AM62x SoC commit ce27f7f9e328c8582a169f97f1466976561f1
("arm64: dts: ti: k3-am62-wakeup: Configure ti-sysc for wkup_uart0"),
The devices in the wkup domain are capable of waking up the system from
suspend. We can configure the wkup domain devices in a generic way using
the ti-sysc interconnect target module driver like we have done with the
earlier TI SoCs.

As ti-sysc manages the SYSCONFIG related registers independent of the
child hardware device, the wake-up configuration is also set even if
wkup_uart0 is reserved by sysfw.

The wkup_uart0 device has interconnect target module register mapping like
dra7 wkup uart. There is a 1 MB interconnect target range with one uart IP
block in the target module. The power domain and clock affects the whole
interconnect target module.

Note we change the functional clock name to follow the ti-sysc binding
and use "fck" instead of "fclk".

Also note that we need to disable the target module reset as noted by
Markus. Otherwise the sysfw using wkup_uart0 can get confused on some
devices leading to boot time issues such as mbox timeouts.

Signed-off-by: Vibhore Vardhan <vibhore@ti.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
[d-gole@ti.com: Reworded the entire commit message]
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20241231-am62a-dt-ti-sysc-wkup-v1-1-a9b0d18a2649@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j722s-evm: Enable PMIC

Add support for TPS6522x PMIC family on wakeup I2C0 bus.
This device provides regulators (bucks and LDOs), along with
GPIOs, and monitors SOC's MCU error si

arm64: dts: ti: k3-j722s-evm: Enable PMIC

Add support for TPS6522x PMIC family on wakeup I2C0 bus.
This device provides regulators (bucks and LDOs), along with
GPIOs, and monitors SOC's MCU error signal.

Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20250102103814.102499-1-u-kumar1@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am69-sk: Add USB SuperSpeed support

AM69 SK board has two stacked USB3 connectors:
1. USB3 (Stacked TypeA + TypeC)
2. USB3 TypeA Hub interfaced through TUSB8041.

The board

arm64: dts: ti: k3-am69-sk: Add USB SuperSpeed support

AM69 SK board has two stacked USB3 connectors:
1. USB3 (Stacked TypeA + TypeC)
2. USB3 TypeA Hub interfaced through TUSB8041.

The board uses SERDES0 Lane 3 for USB3 IP. So update the
SerDes lane info for PCIe and USB. Add the pin mux data
and enable USB 3.0 support with its respective SERDES settings.

Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
Signed-off-by: Enric Balletbo i Serra <eballetb@redhat.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20250108-am69sk-dt-usb-v3-1-bb4981534754@redhat.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am625-beagleplay: Fix DP83TD510E reset time

The reset deassert time for the DP83TD510E is incorrectly set to
60000us, while the datasheet states that the minimum time required
aft

arm64: dts: ti: k3-am625-beagleplay: Fix DP83TD510E reset time

The reset deassert time for the DP83TD510E is incorrectly set to
60000us, while the datasheet states that the minimum time required
after an hard reset is 30us (while 60ms is the time required for the
Power-On Reset after supply stabilization). The error probably arose
from the two timings being indicated by the same symbol (T2).

Lower the required time to 35us, aligning it to the value required for
the PHY to complete the reset AND to be able to accept the RMII master
clock. This saves ~60ms on boot if the MDIO driver is built-in.

Signed-off-by: Francesco Valla <francesco@valla.it>
Link: https://lore.kernel.org/r/20250105162630.243899-1-francesco@valla.it
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am642-hummingboard-t: Convert overlay to board dts

SolidRun HummingBoard-T has two options for M.2 connector, supporting
either PCI-E or USB-3.1 Gen 1 - depending on configuration

arm64: dts: ti: k3-am642-hummingboard-t: Convert overlay to board dts

SolidRun HummingBoard-T has two options for M.2 connector, supporting
either PCI-E or USB-3.1 Gen 1 - depending on configuration of a mux
on the serdes lane.
The required configurations in device-tree were modeled as overlays.

The USB-3.1 overlay uses /delete-property/ to unset a boolean property
on the usb controller limiting it to USB-2.0 by default.
Overlays can not delete a property from the base dtb, therefore this
overlay is at this time useless.

Convert both overlays into full dts by including the base board dts.
While the pcie overlay was functional, both are converted for a
consistent user experience when selecting between the two mutually
exclusive configurations.

Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Closes: https://lore.kernel.org/linux-devicetree/CAMuHMdXTgpTnJ9U7egC2XjFXXNZ5uiY1O+WxNd6LPJW5Rs5KTw@mail.gmail.com
Fixes: bbef42084cc1 ("arm64: dts: ti: hummingboard-t: add overlays for m.2 pci-e and usb-3")
Signed-off-by: Josua Mayer <josua@solid-run.com>
Link: https://lore.kernel.org/r/20250101-am64-hb-fix-overlay-v2-1-78143f5da28c@solid-run.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am69-sk: Add overlay for PCIE0 Endpoint Mode

Add overlay to enable the PCIE0 instance of PCIe on AM69-SK in Endpoint
mode of operation.

Signed-off-by: Siddharth Vadapalli <s-vada

arm64: dts: ti: k3-am69-sk: Add overlay for PCIE0 Endpoint Mode

Add overlay to enable the PCIE0 instance of PCIe on AM69-SK in Endpoint
mode of operation.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20241205105041.749576-5-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am68-sk-base-board: Add overlay for PCIE1 Endpoint Mode

Add overlay to enable the PCIE1 instance of PCIe on AM68-SK-Base-Board in
Endpoint mode of operation. PCIE1 on AM68-SK-Base

arm64: dts: ti: k3-am68-sk-base-board: Add overlay for PCIE1 Endpoint Mode

Add overlay to enable the PCIE1 instance of PCIe on AM68-SK-Base-Board in
Endpoint mode of operation. PCIE1 on AM68-SK-Base-Board supports x2 Lane
operation unlike its counterpart on J721S2-EVM which supports x1 Lane.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20241205105041.749576-4-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j721e-evm: Add overlay for PCIE1 Endpoint Mode

Add overlay to enable the PCIE1 instance of PCIe on J721E-EVM in Endpoint
mode of operation. Additionally, in order to support both

arm64: dts: ti: k3-j721e-evm: Add overlay for PCIE1 Endpoint Mode

Add overlay to enable the PCIE1 instance of PCIe on J721E-EVM in Endpoint
mode of operation. Additionally, in order to support both PCIE0 and PCIE1
in Endpoint Mode of operation, enable applying device-tree overlays on
"k3-j721e-evm-pcie0-ep.dtb", thereby allowing the overlay for PCIE1 in
Endpoint mode to be applied on the aforementioned DTB.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20241205105041.749576-3-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: Makefile: Fix typo "k3-j7200-evm-pcie1-ep.dtbo"

The list of "dtbs" should contain the resultant "dtb" formed by applying
the "dtbo" overlay on the base "dtb", rather than the "dtbo"

arm64: dts: ti: Makefile: Fix typo "k3-j7200-evm-pcie1-ep.dtbo"

The list of "dtbs" should contain the resultant "dtb" formed by applying
the "dtbo" overlay on the base "dtb", rather than the "dtbo" itself.

Hence, change "k3-j7200-evm-pcie1-ep.dtbo" to "k3-j7200-evm-pcie1-ep.dtb"
in the list of "dtbs".

Fixes: f43ec89bbc83 ("arm64: dts: ti: k3-j7200-evm: Add overlay for PCIE1 Endpoint Mode")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20241205105041.749576-2-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j7200: Add node to disable loopback connection

CTRLMMR_MCU_SPI1_CTRL register controls if MCU_SPI1 is directly
connected to SPI3 in the MAIN Domain (default) or if MCU_SPI1
and SP

arm64: dts: ti: k3-j7200: Add node to disable loopback connection

CTRLMMR_MCU_SPI1_CTRL register controls if MCU_SPI1 is directly
connected to SPI3 in the MAIN Domain (default) or if MCU_SPI1
and SPI3 are independently pinned out. By default, the field
SPI1_LINKDIS (Bit 0) is set to 0h. In order to disable the direct
connection, the SPI1_LINKDIS (Bit 0) needs to be set to 1h. Model
this functionality as a "reg-mux" device and based on the idle-state
property, enable/disable the connection bewtween MCU_SPI1 and MAIN_SPI3.

The register field description has been referred from J7200 TRM [1]
(Table 5-517. CTRLMMR_MCU_SPI1_CTRL Register Field Descriptions).

[1] https://www.ti.com/lit/pdf/spruiu1

Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Link: https://lore.kernel.org/r/20241127075644.210759-1-a-dutta@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j784s4: Use ti,j7200-padconf compatible

Like on j7200, pinctrl contexts shall be saved and restored during
suspend-to-ram.

So use ti,j7200-padconf compatible.

Signed-off-by: Tho

arm64: dts: ti: k3-j784s4: Use ti,j7200-padconf compatible

Like on j7200, pinctrl contexts shall be saved and restored during
suspend-to-ram.

So use ti,j7200-padconf compatible.

Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Link: https://lore.kernel.org/r/20241230-j784s4-s2r-pinctrl-v2-1-35039fafe2ca@bootlin.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am62p-j722s-common-main: Enable USB0 for DFU boot

Add the "bootph-all" property to the "usb0" device-tree node. This is
required for the USB0 instance of USB to be functional at a

arm64: dts: ti: k3-am62p-j722s-common-main: Enable USB0 for DFU boot

Add the "bootph-all" property to the "usb0" device-tree node. This is
required for the USB0 instance of USB to be functional at all stages
of USB DFU boot.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20241220054550.153360-1-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am62a: Remove duplicate GICR reg

The GIC Redistributor control range is mapped twice. Remove the extra
entry from the reg range.

Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce A

arm64: dts: ti: k3-am62a: Remove duplicate GICR reg

The GIC Redistributor control range is mapped twice. Remove the extra
entry from the reg range.

Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs")
Reported-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20241210-am62-gic-fixup-v1-2-758b4d5b4a0a@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am62: Remove duplicate GICR reg

The GIC Redistributor control register range is mapped twice. Remove
the extra entry from the reg range.

Fixes: f1d17330a5be ("arm64: dts: ti: Int

arm64: dts: ti: k3-am62: Remove duplicate GICR reg

The GIC Redistributor control register range is mapped twice. Remove
the extra entry from the reg range.

Fixes: f1d17330a5be ("arm64: dts: ti: Introduce base support for AM62x SoC")
Reported-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20241210-am62-gic-fixup-v1-1-758b4d5b4a0a@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am67a-beagley-ai: Add remote processor nodes

Add nodes for the R5F and C7x cores on the SoC. This includes the mailbox
and memory carveouts used by these remote cores.

Signed-off

arm64: dts: ti: k3-am67a-beagley-ai: Add remote processor nodes

Add nodes for the R5F and C7x cores on the SoC. This includes the mailbox
and memory carveouts used by these remote cores.

Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20241203174114.94751-2-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am62p: Enable Mailbox nodes at the board level

Mailbox nodes defined in the top-level J722s/AM62p SoC dtsi files are
incomplete and may not be functional unless they are extended

arm64: dts: ti: k3-am62p: Enable Mailbox nodes at the board level

Mailbox nodes defined in the top-level J722s/AM62p SoC dtsi files are
incomplete and may not be functional unless they are extended with a
chosen interrupt and connection to a remote processor.

Disable the Mailbox nodes in the dtsi files and only enable the ones
that are actually used on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20241203174114.94751-1-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am625-sk: Remove M4 mailbox node redefinition

This node is already defined in the included k3-am62x-sk-common.dtsi.
Remove this redefinition.

Signed-off-by: Andrew Davis <afd@ti.

arm64: dts: ti: k3-am625-sk: Remove M4 mailbox node redefinition

This node is already defined in the included k3-am62x-sk-common.dtsi.
Remove this redefinition.

Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20241203164031.20211-1-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j722s-evm: Enable support for mcu_i2c0

Enable support for mcu_i2c0 and add pinmux required to bring out the
mcu_i2c0 signals on 40-pin RPi expansion header on the J722S EVM.

Sign

arm64: dts: ti: k3-j722s-evm: Enable support for mcu_i2c0

Enable support for mcu_i2c0 and add pinmux required to bring out the
mcu_i2c0 signals on 40-pin RPi expansion header on the J722S EVM.

Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Signed-off-by: Shreyash Sinha <s-sinha@ti.com>
Reviewed-by: Prasanth Babu Mantena <p-mantena@ti.com>
Link: https://lore.kernel.org/r/20241105091224.23453-1-b-kapoor@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am62x-sk-common: Add bootph-all property in cpsw_mac_syscon node

Ethernet boot requires CPSW node to be present starting from R5 SPL stage.
Add bootph-all property in CPSW MAC's e

arm64: dts: ti: k3-am62x-sk-common: Add bootph-all property in cpsw_mac_syscon node

Ethernet boot requires CPSW node to be present starting from R5 SPL stage.
Add bootph-all property in CPSW MAC's eFuse node cpsw_mac_syscon to enable
this node during SPL stage along with later boot stages so that CPSW port
will get static MAC address.

Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
Link: https://lore.kernel.org/r/20241114165331.1279065-1-c-vankar@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: Remove unused and undocumented "ti,(rx|tx)-fifo-depth" properties

Remove "ti,(rx|tx)-fifo-depth" properties which are both unused in the
kernel and undocumented. Most likely they are

arm64: dts: ti: Remove unused and undocumented "ti,(rx|tx)-fifo-depth" properties

Remove "ti,(rx|tx)-fifo-depth" properties which are both unused in the
kernel and undocumented. Most likely they are leftovers from downstream.

There are similar properties, but DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
represents the default value so adding them is not necessary.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241115193359.3618020-1-robh@kernel.org
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am64-main: Switch ICSSG clock to core clock

ICSSG has 7 available clocks per instance. Add all the cloks to ICSSG
nodes. ICSSG currently uses ICSSG_ICLK (clk id 20) which operates

arm64: dts: ti: k3-am64-main: Switch ICSSG clock to core clock

ICSSG has 7 available clocks per instance. Add all the cloks to ICSSG
nodes. ICSSG currently uses ICSSG_ICLK (clk id 20) which operates at
250MHz. Switch ICSSG clock to ICSSG_CORE clock (clk id 0) which operates at
333MHz.

ICSSG_CORE clock will help get the most out of ICSSG as more cycles are
needed to fully support all ICSSG features.

This commit also changes assigned-clock-parents of coreclk-mux to
ICSSG_CORE clock from ICSSG_ICLK.

Performance update in dual mac mode
With ICSSG_CORE Clk @ 333MHz
Tx throughput - 934 Mbps
Rx throughput - 914 Mbps,

With ICSSG_ICLK clk @ 250MHz,
Tx throughput - 920 Mbps
Rx throughput - 706 Mbps

Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20241113110955.3876045-3-danishanwar@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am69-sk: Mark tps659413 regulators as bootph-all

In order for the MCU domain to access this PMIC, a regulator
needs to be marked appropriately otherwise it is not seen by SPL and

arm64: dts: ti: k3-am69-sk: Mark tps659413 regulators as bootph-all

In order for the MCU domain to access this PMIC, a regulator
needs to be marked appropriately otherwise it is not seen by SPL and
therefore not configured.

This is necessary if the MCU domain is to program the TPS6594 MCU ESM
state machine, which is required to wire up the watchdog in a manner
that will reset the board.

Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Beleswar Padhi <b-padhi@ti.com>
Tested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Enric Balletbo i Serra <eballetb@redhat.com>
Link: https://lore.kernel.org/r/20241113-b4-j784s4-tps6594-bootph-v4-2-102ddaa1bdc6@redhat.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j784s4-evm: Mark tps659413 regulators as bootph-all

In order for the MCU domain to access this PMIC, a regulator
needs to be marked appropriately otherwise it is not seen by SPL a

arm64: dts: ti: k3-j784s4-evm: Mark tps659413 regulators as bootph-all

In order for the MCU domain to access this PMIC, a regulator
needs to be marked appropriately otherwise it is not seen by SPL and
therefore not configured.

This is necessary if the MCU domain is to program the TPS6594 MCU ESM
state machine, which is required to wire up the watchdog in a manner
that will reset the board.

Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Beleswar Padhi <b-padhi@ti.com>
Tested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Enric Balletbo i Serra <eballetb@redhat.com>
Link: https://lore.kernel.org/r/20241113-b4-j784s4-tps6594-bootph-v4-1-102ddaa1bdc6@redhat.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am62x-sk-common: Support SoC wakeup using USB1 wakeup

After the SoC has entered the Deep Sleep mode, USB1 can be used to wakeup
the SoC based on USB events triggered by USB device

arm64: dts: ti: k3-am62x-sk-common: Support SoC wakeup using USB1 wakeup

After the SoC has entered the Deep Sleep mode, USB1 can be used to wakeup
the SoC based on USB events triggered by USB devices. This requires that
the pin corresponding to the Type-A connector remains pulled up even after
the SoC has entered the Deep Sleep mode. Hence, enable Deep Sleep pullup /
pulldown selection for the USB1_DRVVBUS pin and set its Deep Sleep state to
PULL_UP.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20241205120134.754664-3-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-pinctrl: Introduce deep sleep macros

The behavior of pins in deep sleep mode can be configured by programming
the corresponding bits in the respective Pad Configuration register.

arm64: dts: ti: k3-pinctrl: Introduce deep sleep macros

The behavior of pins in deep sleep mode can be configured by programming
the corresponding bits in the respective Pad Configuration register. Add
macros to support this.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20241205120134.754664-2-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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