| ff98c983 | 13-May-2026 |
Tze Yee Ng <tze.yee.ng@altera.com> |
arm64: dts: socfpga: use consistent QSPI boot partition label
Several SoCFPGA board DTS files labeled the first QSPI MTD partition
(qspi_boot / partition@0 under fixed-partitions) as "u-boot" while
arm64: dts: socfpga: use consistent QSPI boot partition label
Several SoCFPGA board DTS files labeled the first QSPI MTD partition
(qspi_boot / partition@0 under fixed-partitions) as "u-boot" while
others already used "Boot and fpga data". Align the QSPI boot
partition label only so naming matches the combined boot + FPGA
image layout and stays consistent across Agilex, N5X, and Stratix 10
SoCDK variants.
No QSPI partition layout or reg properties are changed.
Signed-off-by: Tze Yee Ng <tze.yee.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 0764f42a | 26-Jun-2026 |
Dinh Nguyen <dinguyen@kernel.org> |
arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2
Populate the gmac1 and gmac2 interrupt list to support 8 TX/RX queue
pairs.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.o
arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2
Populate the gmac1 and gmac2 interrupt list to support 8 TX/RX queue
pairs.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: no changes
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| 5eb1916e | 25-Jun-2026 |
Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> |
arm64: dts: socfpga: agilex72: Add initial device tree
Add initial device tree support for the Intel SoCFPGA Agilex72
platform. This introduces the SoC DTSI and the SoCDK board DTS as
the first upst
arm64: dts: socfpga: agilex72: Add initial device tree
Add initial device tree support for the Intel SoCFPGA Agilex72
platform. This introduces the SoC DTSI and the SoCDK board DTS as
the first upstream submission for this platform.
The Agilex72 SoC features a heterogeneous CPU cluster with
Cortex-A520 and Cortex-A720 cores, and includes an SMMU v3 for
memory management.
Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 501a9828 | 24-Jun-2026 |
Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> |
arm64: dts: socfpga: agilex5: Add dma-coherent to XGMAC nodes
The SMMU is enabled and transactions going through it are cache
coherent. Add the dma-coherent property to the XGMAC nodes to prevent
re
arm64: dts: socfpga: agilex5: Add dma-coherent to XGMAC nodes
The SMMU is enabled and transactions going through it are cache
coherent. Add the dma-coherent property to the XGMAC nodes to prevent
redundant cache flush/invalidate operations and potential stale data
issues.
Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 10cf797f | 24-Jun-2026 |
Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> |
arm64: dts: socfpga: agilex5: Enable the SMMU
The SMMU is disabled in socfpga_agilex5.dtsi. The SoC uses a different
memory-mapped base address for its peripherals, which requires the SMMU
to be act
arm64: dts: socfpga: agilex5: Enable the SMMU
The SMMU is disabled in socfpga_agilex5.dtsi. The SoC uses a different
memory-mapped base address for its peripherals, which requires the SMMU
to be active so that the Secure Device Manager (SDM) can correctly
access those regions through address translation.
Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| ea3aec95 | 10-Jun-2026 |
Geert Uytterhoeven <geert+renesas@glider.be> |
arm64: dts: intel: keembay: Always use decimal interrupts
Replace the sole hexadecimal interrupt number by a decimal number, for
consistency with all other interrupt numbers.
Signed-off-by: Geert U
arm64: dts: intel: keembay: Always use decimal interrupts
Replace the sole hexadecimal interrupt number by a decimal number, for
consistency with all other interrupt numbers.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| c5637e5c | 07-May-2026 |
Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> |
arm64: dts: socfpga: agilex5: Fix phy-mode to rgmii as HW provides clock delay
The Agilex5 SoC provides RGMII TX/RX clock delay compensation through
its integrated I/O hardware. Using phy-mode = "rg
arm64: dts: socfpga: agilex5: Fix phy-mode to rgmii as HW provides clock delay
The Agilex5 SoC provides RGMII TX/RX clock delay compensation through
its integrated I/O hardware. Using phy-mode = "rgmii-id" instructs the
MAC driver to additionally insert internal TX/RX delays, resulting in
double delay being applied and causing Ethernet link timing issues.
Change phy-mode to "rgmii" across all Agilex5 device tree files to
reflect that the clock delay is already handled by the hardware and
no additional software-inserted delay is required. Add an inline comment
to satisfy checkpatch and document the hardware-provided delay.
Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 90d083b0 | 06-May-2026 |
Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com> |
arm64: dts: socfpga: agilex5: update data-width for dmac
Update data-width property for dmac to 3 which is 64 bits to match value
configured in the hardware register.
Signed-off-by: Adrian Ng Ho Yi
arm64: dts: socfpga: agilex5: update data-width for dmac
Update data-width property for dmac to 3 which is 64 bits to match value
configured in the hardware register.
Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 49a2a555 | 05-May-2026 |
Adrian Ng Ho Yin <adrianhoyin.ng@altera.com> |
arm64: dts: socfpga: agilex3: set alias for i3c controller
Agilex3 SoCFPGA have 2 i3c controllers, a main master and a secondary
master. Setting the alias for both i3c controllers to prevent bus id
arm64: dts: socfpga: agilex3: set alias for i3c controller
Agilex3 SoCFPGA have 2 i3c controllers, a main master and a secondary
master. Setting the alias for both i3c controllers to prevent bus id
contention when both controllers are enabled which results in driver
probe failures.
Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 5b80089b | 05-May-2026 |
Adrian Ng Ho Yin <adrianhoyin.ng@altera.com> |
arm64: dts: socfpga: agilex5: set alias for i3c controllers
Agilex5 SoCFPGA variants and derivatives have 2 i3c controllers, a main
master and a secondary master. Setting the alias for both i3c cont
arm64: dts: socfpga: agilex5: set alias for i3c controllers
Agilex5 SoCFPGA variants and derivatives have 2 i3c controllers, a main
master and a secondary master. Setting the alias for both i3c controllers
to prevent bus id contention when both controllers are enabled which
results in driver probe failures.
Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 95cc767d | 26-Jan-2026 |
Ng Tze Yee <tzeyee.ng@altera.com> |
arm64: dts: socfpga: agilex: add emmc support
The Agilex devkit supports a separate eMMC daughter card. The
eMMC daughter card replaces the SDMMC slot that is on the default
daughter card and thus r
arm64: dts: socfpga: agilex: add emmc support
The Agilex devkit supports a separate eMMC daughter card. The
eMMC daughter card replaces the SDMMC slot that is on the default
daughter card and thus requires a separate board dts file.
Signed-off-by: Ng Tze Yee <tzeyee.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 4e6e93df | 29-Dec-2025 |
Khairul Anuar Romli <khairul.anuar.romli@altera.com> |
arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node
Move dma-controller node under simple-bus node to allow bus node specific
property able to be properly defined. This is
arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node
Move dma-controller node under simple-bus node to allow bus node specific
property able to be properly defined. This is require to fulfill Agilex5
bus limitation that is limited to 40-addressable-bit.
Update the compatible string for the DMA controller nodes in the Agilex5
device tree from the generic "snps,axi-dma-1.01a" to the platform-specific
"altr,agilex5-axi-dma". Add fallback capability to ensure driver is able
to initialize properly.
This change enables the use of platform-specific features and constraints
in the driver, such as setting a 40-bit DMA addressable mask through
dma-ranges, which is required for Agilex5. It also aligns with the updated
device tree bindings and driver support for this compatible string.
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 67c1d789 | 04-Dec-2025 |
Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> |
arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes
To enable SMMU integration, populate the iommus property to the ethernet
device-tree node.
Signed-off-by: Nazim Amirul <muhammad
arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes
To enable SMMU integration, populate the iommus property to the ethernet
device-tree node.
Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| ebb6a68a | 02-Dec-2025 |
Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> |
arm64: dts: socfpga: agilex5: add support for modular board
The Agilex5 Modular board consists of a compute module (Agilex5 SoCFPGA)
attached to a carrier board that provides PCIe and additional sys
arm64: dts: socfpga: agilex5: add support for modular board
The Agilex5 Modular board consists of a compute module (Agilex5 SoCFPGA)
attached to a carrier board that provides PCIe and additional system
interfaces.
Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 38eff72f | 14-Nov-2025 |
Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> |
arm64: dts: socfpga: agilex5: update qspi partitions for 013b board
Update qspi flash partitions to support Remote System Update (RSU).
Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara
arm64: dts: socfpga: agilex5: update qspi partitions for 013b board
Update qspi flash partitions to support Remote System Update (RSU).
Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 44964e81 | 14-Nov-2025 |
Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> |
arm64: dts: socfpga: add Agilex3 board
Agilex3 SoCFPGA development kit is a small form factor board similar to
Agilex5 013b board. Agilex3 is derived from Agilex5 SoCFPGA, with the main
difference o
arm64: dts: socfpga: add Agilex3 board
Agilex3 SoCFPGA development kit is a small form factor board similar to
Agilex5 013b board. Agilex3 is derived from Agilex5 SoCFPGA, with the main
difference of CPU cores — Agilex3 has 2 cores compared to 4 in Agilex5.
Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 5e7235d1 | 04-Nov-2025 |
Adrian Ng Ho Yin <adrianhoyin.ng@altera.com> |
arm64: dts: intel: agilex5: Add Altera compatible for I3C controllers
Add the "altr,agilex5-dw-i3c-master" compatible string to the
I3C controller nodes on the Agilex5 SoCFPGA platform.
Signed-off-
arm64: dts: intel: agilex5: Add Altera compatible for I3C controllers
Add the "altr,agilex5-dw-i3c-master" compatible string to the
I3C controller nodes on the Agilex5 SoCFPGA platform.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| 1aa4ee53 | 07-Nov-2025 |
Khairul Anuar Romli <khairul.anuar.romli@altera.com> |
arm64: dts: socfpga: Add Agilex5 SVC node with memory region
Introduce the Stratix10 SoC Service Layer (SVC) node for Agilex5 SoCs. This
node includes the compatible string "intel,agilex5-svc" and r
arm64: dts: socfpga: Add Agilex5 SVC node with memory region
Introduce the Stratix10 SoC Service Layer (SVC) node for Agilex5 SoCs. This
node includes the compatible string "intel,agilex5-svc" and references a
reserved memory region used for communication with the Secure Device
Manager (SDM).
Agilex5 introduces changes in how reserved memory is mapped and accessed
compared to previous SoC generations. This commit updates the device tree
structure to support Agilex5-specific handling of the SVC interface.
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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