arm64: dts: socfpga: agilex5: Fix phy-mode to rgmii as HW provides clock delay

The Agilex5 SoC provides RGMII TX/RX clock delay compensation through
its integrated I/O hardware. Using phy-mode = "rg

arm64: dts: socfpga: agilex5: Fix phy-mode to rgmii as HW provides clock delay

The Agilex5 SoC provides RGMII TX/RX clock delay compensation through
its integrated I/O hardware. Using phy-mode = "rgmii-id" instructs the
MAC driver to additionally insert internal TX/RX delays, resulting in
double delay being applied and causing Ethernet link timing issues.

Change phy-mode to "rgmii" across all Agilex5 device tree files to
reflect that the clock delay is already handled by the hardware and
no additional software-inserted delay is required. Add an inline comment
to satisfy checkpatch and document the hardware-provided delay.

Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

show more ...

arm64: dts: socfpga: agilex5: update data-width for dmac

Update data-width property for dmac to 3 which is 64 bits to match value
configured in the hardware register.

Signed-off-by: Adrian Ng Ho Yi

arm64: dts: socfpga: agilex5: update data-width for dmac

Update data-width property for dmac to 3 which is 64 bits to match value
configured in the hardware register.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

show more ...

arm64: dts: socfpga: agilex3: set alias for i3c controller

Agilex3 SoCFPGA have 2 i3c controllers, a main master and a secondary
master. Setting the alias for both i3c controllers to prevent bus id

arm64: dts: socfpga: agilex3: set alias for i3c controller

Agilex3 SoCFPGA have 2 i3c controllers, a main master and a secondary
master. Setting the alias for both i3c controllers to prevent bus id
contention when both controllers are enabled which results in driver
probe failures.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

show more ...

arm64: dts: socfpga: agilex5: set alias for i3c controllers

Agilex5 SoCFPGA variants and derivatives have 2 i3c controllers, a main
master and a secondary master. Setting the alias for both i3c cont

arm64: dts: socfpga: agilex5: set alias for i3c controllers

Agilex5 SoCFPGA variants and derivatives have 2 i3c controllers, a main
master and a secondary master. Setting the alias for both i3c controllers
to prevent bus id contention when both controllers are enabled which
results in driver probe failures.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

show more ...

arm64: dts: socfpga: agilex7m: Add SoCFPGA Agilex7-M devkit

The Agilex7-M devkit contains an Agilex7M SoC, which is a newly branded
version of the original Agilex SoC. The Agilex7M core peripherals

arm64: dts: socfpga: agilex7m: Add SoCFPGA Agilex7-M devkit

The Agilex7-M devkit contains an Agilex7M SoC, which is a newly branded
version of the original Agilex SoC. The Agilex7M core peripherals are
identical to the Agilex SoC.

We can re-use the socfpga_agilex.dtsi for this devkit. The Agilex7-M
devkit supports PCIE 5.0(x16), DDR4, DDR5, LPDDR5 and does not have QSPI.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

show more ...