| 3d7bd20e | 02-Mar-2026 |
André Draszik <andre.draszik@linaro.org> |
arm64: dts: exynos: gs101-pixel-common: add Maxim MAX77759 fuel gauge
On Pixel 6 (and Pro), a MAX77759 companion PMIC for USB Type-C
applications is used, which contains four functional blocks (at
d
arm64: dts: exynos: gs101-pixel-common: add Maxim MAX77759 fuel gauge
On Pixel 6 (and Pro), a MAX77759 companion PMIC for USB Type-C
applications is used, which contains four functional blocks (at
distinct I2C addresses):
* top (including GPIO & NVMEM)
* charger
* fuel gauge
* TCPCi
This change adds the fuel gauge.
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://patch.msgid.link/20260302-max77759-fg-dts-v2-1-12f1109a6fee@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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| 024d8f4a | 13-Jan-2026 |
Peter Griffin <peter.griffin@linaro.org> |
arm64: dts: exynos: gs101: add cmu_dpu and sysreg_dpu dt nodes
Enable the cmu_dpu clock management unit. It feeds some of the display
IPs. Additionally add the sysreg_dpu node which contains the
BUS
arm64: dts: exynos: gs101: add cmu_dpu and sysreg_dpu dt nodes
Enable the cmu_dpu clock management unit. It feeds some of the display
IPs. Additionally add the sysreg_dpu node which contains the
BUSCOMPONENT_DRCG_EN and MEMCLK registers required by cmu_dpu to enable
dynamic root clock gating of bus components.
Reviewed-by: André Draszik <andre.draszik@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://patch.msgid.link/20260113-dpu-clocks-v3-5-cb85424f2c72@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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| 9afdf3e1 | 22-Dec-2025 |
Tudor Ambarus <tudor.ambarus@linaro.org> |
arm64: dts: exynos: gs101: add OTP node
Add the OTP controller node.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: André Draszik <andre.draszik@linaro.org>
Link: https://patc
arm64: dts: exynos: gs101: add OTP node
Add the OTP controller node.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: André Draszik <andre.draszik@linaro.org>
Link: https://patch.msgid.link/20251222-gs101-chipid-v4-5-aa8e20ce7bb3@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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| 01272f05 | 22-Dec-2025 |
Peter Griffin <peter.griffin@linaro.org> |
arm64: dts: exynos: gs101: add samsung,sysreg property to CMU nodes
With the exception of cmu_top, each CMU has a corresponding sysreg bank
that contains the BUSCOMPONENT_DRCG_EN and optional MEMCLK
arm64: dts: exynos: gs101: add samsung,sysreg property to CMU nodes
With the exception of cmu_top, each CMU has a corresponding sysreg bank
that contains the BUSCOMPONENT_DRCG_EN and optional MEMCLK registers.
The BUSCOMPONENT_DRCG_EN register enables dynamic root clock gating of
bus components and MEMCLK gates the sram clock.
Now the clock driver supports automatic clock mode, provide the
samsung,sysreg property so the driver can enable dynamic root clock
gating of bus components and gate sram clock.
Note without the property specified the driver simply falls back to
previous behaviour of not configuring these registers so it is not an ABI
break.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://patch.msgid.link/20251222-automatic-clocks-v7-2-fec86fa89874@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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| a21d38b5 | 14-Nov-2025 |
Peter Griffin <peter.griffin@linaro.org> |
arm64: dts: exynos: gs101: remove syscon compatible from pmu node
Since commit ba5095ebbc7a ("mfd: syscon: Allow syscon nodes without a
"syscon" compatible") it is possible to register a regmap with
arm64: dts: exynos: gs101: remove syscon compatible from pmu node
Since commit ba5095ebbc7a ("mfd: syscon: Allow syscon nodes without a
"syscon" compatible") it is possible to register a regmap without the
syscon compatible in the node.
As mentioned in that commit, it's not correct to claim we are compatible
with syscon, as a MMIO regmap created by syscon won't work. Removing the
syscon compatible means syscon driver won't ever create a mmio regmap.
Note this isn't usually an issue today as exynos-pmu runs at an early
initcall so the custom regmap will have been registered first. However
changes proposed in [1] will bring -EPROBE_DEFER support to syscon allowing
this mechanism to be more robust, especially in highly modularized systems.
Technically this is a ABI break but no other platforms are
affected. Additionally (with the benefit of hindsight) a MMIO syscon has
never worked for PMU register writes, thus the ABI break is justified.
Link: https://lore.kernel.org/lkml/aQdHmrchkmOr34r3@stanley.mountain/ [1]
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://patch.msgid.link/20251114-remove-pmu-syscon-compat-v2-2-9496e8c496c7@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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| 4348c22a | 13-Oct-2025 |
Peter Griffin <peter.griffin@linaro.org> |
arm64: dts: exynos: gs101: fix sysreg_apm reg property
Both the start address and size are incorrect for the apm_sysreg DT
node. Update to match the TRM (rather than how it was defined
downstream).
arm64: dts: exynos: gs101: fix sysreg_apm reg property
Both the start address and size are incorrect for the apm_sysreg DT
node. Update to match the TRM (rather than how it was defined
downstream).
Fixes: ea89fdf24fd9 ("arm64: dts: exynos: google: Add initial Google gs101 SoC support")
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: André Draszik <andre.draszik@linaro.org>
Link: https://patch.msgid.link/20251013-automatic-clocks-v1-5-72851ee00300@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| ddb2a168 | 13-Oct-2025 |
Peter Griffin <peter.griffin@linaro.org> |
arm64: dts: exynos: gs101: fix clock module unit reg sizes
The memory map lists each clock module unit as having a size of
0x10000. Additionally there are some undocumented registers in this region
arm64: dts: exynos: gs101: fix clock module unit reg sizes
The memory map lists each clock module unit as having a size of
0x10000. Additionally there are some undocumented registers in this region
that need to be used for automatic clock gating mode. Some of those
registers also need to be saved/restored on suspend & resume.
Fixes: 86124c76683e ("arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller")
Fixes: 4982a4a2092e ("arm64: dts: exynos: gs101: enable cmu-hsi0 clock controller")
Fixes: 7d66d98b5bf3 ("arm64: dts: exynos: gs101: enable cmu-peric1 clock controller")
Fixes: e62c706f3aa0 ("arm64: dts: exynos: gs101: enable cmu-peric0 clock controller")
Fixes: ea89fdf24fd9 ("arm64: dts: exynos: google: Add initial Google gs101 SoC support")
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: André Draszik <andre.draszik@linaro.org>
Link: https://patch.msgid.link/20251013-automatic-clocks-v1-4-72851ee00300@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 08d9d0d9 | 13-Oct-2025 |
Peter Griffin <peter.griffin@linaro.org> |
arm64: dts: exynos: gs101: add sysreg_misc and sysreg_hsi0 nodes
Add syscon DT node for the hsi0 and misc sysreg controllers. These will
be referenced by their respective CMU nodes in future patches
arm64: dts: exynos: gs101: add sysreg_misc and sysreg_hsi0 nodes
Add syscon DT node for the hsi0 and misc sysreg controllers. These will
be referenced by their respective CMU nodes in future patches.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: André Draszik <andre.draszik@linaro.org>
Link: https://patch.msgid.link/20251013-automatic-clocks-v1-3-72851ee00300@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| bb103f6c | 24-Sep-2025 |
Tudor Ambarus <tudor.ambarus@linaro.org> |
arm64: dts: exynos: gs101: add OPPs
Add operating performance points (OPPs).
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by:
arm64: dts: exynos: gs101: add OPPs
Add operating performance points (OPPs).
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org> # on gs101-oriole
Link: https://patch.msgid.link/20250924-acpm-dvfs-dt-v4-3-3106d49e03f5@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 025707fa | 24-Sep-2025 |
Tudor Ambarus <tudor.ambarus@linaro.org> |
arm64: dts: exynos: gs101: add CPU clocks
Add the GS101 CPU clocks exposed through the ACPM protocol.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Peter Griffin <peter.griff
arm64: dts: exynos: gs101: add CPU clocks
Add the GS101 CPU clocks exposed through the ACPM protocol.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org> # on gs101-oriole
Link: https://patch.msgid.link/20250924-acpm-dvfs-dt-v4-2-3106d49e03f5@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 2e96df32 | 24-Sep-2025 |
Tudor Ambarus <tudor.ambarus@linaro.org> |
arm64: dts: exynos: gs101: add #clock-cells to the ACPM protocol node
Make the ACPM node a clock provider by adding the mandatory
"#clock-cells" property, which allows devices to reference
its clock
arm64: dts: exynos: gs101: add #clock-cells to the ACPM protocol node
Make the ACPM node a clock provider by adding the mandatory
"#clock-cells" property, which allows devices to reference
its clock outputs.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org> # on gs101-oriole
Link: https://patch.msgid.link/20250924-acpm-dvfs-dt-v4-1-3106d49e03f5@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 98be2d60 | 27-Jun-2025 |
André Draszik <andre.draszik@linaro.org> |
arm64: dts: exynos: gs101: switch to gs101 specific reboot
gs101 (Google Pixel 6 and Pixel 6 Pro) supports cold- and warm-reboot.
Cold-reset is useful because it is more secure, e.g. wiping all RAM
arm64: dts: exynos: gs101: switch to gs101 specific reboot
gs101 (Google Pixel 6 and Pixel 6 Pro) supports cold- and warm-reboot.
Cold-reset is useful because it is more secure, e.g. wiping all RAM
contents, while the warm-reboot allows RAM contents to be retained
across the reboot, e.g. to collect potential crash information.
Add the required DT changes to switch to the gs101-specific reboot
method, which knows how to issue either reset as requested by the OS.
The PMIC plays a role in this as well, so mark it as
'system-power-controller', which in this case ensures that the device
will wake up again after a cold-reboot, ensuring the full power-cycle
is successful.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20250627-gs101-reboot3-v1-3-c3ae49657b1f@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| cb98b8a8 | 27-Jun-2025 |
André Draszik <andre.draszik@linaro.org> |
arm64: dts: exynos: gs101-pixel-common: add main PMIC node
On Pixel 6 (and Pro), a Samsung S2MPG10 is used as main PMIC, which
contains the following functional blocks:
* common / speedy interfa
arm64: dts: exynos: gs101-pixel-common: add main PMIC node
On Pixel 6 (and Pro), a Samsung S2MPG10 is used as main PMIC, which
contains the following functional blocks:
* common / speedy interface
* regulators
* 3 clock outputs
* RTC
* power meters
* GPIO interfaces
This change enables the PMIC itself and the RTC. We're still working on
the remaining parts or waiting for bindings to be merged, hence only a
small subset of the functional is being enabled.
The regulators fall into the same category (still being finalised), but
since the binding requires a 'regulators' node, an empty node is being
added to avoid validation errors at this stage.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20250627-gs101-reboot3-v1-2-c3ae49657b1f@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 4292564c | 14-Mar-2025 |
Peter Griffin <peter.griffin@linaro.org> |
arm64: dts: exynos: gs101: ufs: add dma-coherent property
ufs-exynos driver configures the sysreg shareability as
cacheable for gs101 so we need to set the dma-coherent
property so the descriptors a
arm64: dts: exynos: gs101: ufs: add dma-coherent property
ufs-exynos driver configures the sysreg shareability as
cacheable for gs101 so we need to set the dma-coherent
property so the descriptors are also allocated cacheable.
This fixes the UFS stability issues we have seen with
the upstream UFS driver on gs101.
Fixes: 4c65d7054b4c ("arm64: dts: exynos: gs101: Add ufs and ufs-phy dt nodes")
Cc: stable@vger.kernel.org
Suggested-by: Will McVicker <willmcvicker@google.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Tested-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20250314-ufs-dma-coherent-v1-1-bdf9f9be2919@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 17a3657e | 24-May-2025 |
André Draszik <andre.draszik@linaro.org> |
arm64: dts: exynos: gs101: add dm-verity-device-corrupted syscon-reboot-mode
On gs101, the boot mode is stored both in a syscon register, and in
nvmem.
Add the dm-verity-device-corrupted reboot mod
arm64: dts: exynos: gs101: add dm-verity-device-corrupted syscon-reboot-mode
On gs101, the boot mode is stored both in a syscon register, and in
nvmem.
Add the dm-verity-device-corrupted reboot mode to the syscon-reboot-
based boot mode as well, as both (nvmem & syscon) modes should be in
sync.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20250524-b4-max77759-mfd-dts-v2-4-b479542eb97d@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 4292d182 | 24-May-2025 |
André Draszik <andre.draszik@linaro.org> |
arm64: dts: exynos: gs101-pixel-common: add nvmem-reboot-mode
Add the 'nvmem-reboot-mode' which is used to communicate a requested
boot mode to the boot loader.
Signed-off-by: André Draszik <andre.
arm64: dts: exynos: gs101-pixel-common: add nvmem-reboot-mode
Add the 'nvmem-reboot-mode' which is used to communicate a requested
boot mode to the boot loader.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20250524-b4-max77759-mfd-dts-v2-3-b479542eb97d@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 8deaddf1 | 24-May-2025 |
André Draszik <andre.draszik@linaro.org> |
arm64: dts: exynos: gs101-pixel-common: add Maxim MAX77759 PMIC
On Pixel 6 (and Pro), a MAX77759 companion PMIC for USB Type-C
applications is used, which contains four functional blocks (at
distinc
arm64: dts: exynos: gs101-pixel-common: add Maxim MAX77759 PMIC
On Pixel 6 (and Pro), a MAX77759 companion PMIC for USB Type-C
applications is used, which contains four functional blocks (at
distinct I2C addresses):
* top (including GPIO & NVMEM)
* charger
* fuel gauge
* TCPCi
This change adds the PMIC and the subnodes for the GPIO expander and
NVMEM, and defines the NVMEM layout.
The NVMEM layout is declared such that it matches downstream's
open-coded configuration [1].
Note:
The pinctrl nodes are kept sorted by the 'samsung,pins' property rather
than node name, as I think that makes it easier to look at and to add
new nodes unambiguously in the future. Its label is prefixed with 'if'
(for interface), because there are three PMICs in total in use on
Pixel 6 (Pro).
Link: https://android.googlesource.com/kernel/google-modules/bms/+/96e729a83817/max77759_maxq.c#67 [1]
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20250524-b4-max77759-mfd-dts-v2-2-b479542eb97d@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 73fd2bb6 | 19-Feb-2025 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: exynos: gs101: Change labels to lower-case
DTS coding style expects labels to be lowercase. No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).
Re
arm64: dts: exynos: gs101: Change labels to lower-case
DTS coding style expects labels to be lowercase. No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).
Reviewed-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20250219085726.70824-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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