| 98be2d60 | 27-Jun-2025 |
André Draszik <andre.draszik@linaro.org> |
arm64: dts: exynos: gs101: switch to gs101 specific reboot
gs101 (Google Pixel 6 and Pixel 6 Pro) supports cold- and warm-reboot.
Cold-reset is useful because it is more secure, e.g. wiping all RAM
arm64: dts: exynos: gs101: switch to gs101 specific reboot
gs101 (Google Pixel 6 and Pixel 6 Pro) supports cold- and warm-reboot.
Cold-reset is useful because it is more secure, e.g. wiping all RAM
contents, while the warm-reboot allows RAM contents to be retained
across the reboot, e.g. to collect potential crash information.
Add the required DT changes to switch to the gs101-specific reboot
method, which knows how to issue either reset as requested by the OS.
The PMIC plays a role in this as well, so mark it as
'system-power-controller', which in this case ensures that the device
will wake up again after a cold-reboot, ensuring the full power-cycle
is successful.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20250627-gs101-reboot3-v1-3-c3ae49657b1f@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| cb98b8a8 | 27-Jun-2025 |
André Draszik <andre.draszik@linaro.org> |
arm64: dts: exynos: gs101-pixel-common: add main PMIC node
On Pixel 6 (and Pro), a Samsung S2MPG10 is used as main PMIC, which
contains the following functional blocks:
* common / speedy interfa
arm64: dts: exynos: gs101-pixel-common: add main PMIC node
On Pixel 6 (and Pro), a Samsung S2MPG10 is used as main PMIC, which
contains the following functional blocks:
* common / speedy interface
* regulators
* 3 clock outputs
* RTC
* power meters
* GPIO interfaces
This change enables the PMIC itself and the RTC. We're still working on
the remaining parts or waiting for bindings to be merged, hence only a
small subset of the functional is being enabled.
The regulators fall into the same category (still being finalised), but
since the binding requires a 'regulators' node, an empty node is being
added to avoid validation errors at this stage.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20250627-gs101-reboot3-v1-2-c3ae49657b1f@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 4292564c | 14-Mar-2025 |
Peter Griffin <peter.griffin@linaro.org> |
arm64: dts: exynos: gs101: ufs: add dma-coherent property
ufs-exynos driver configures the sysreg shareability as
cacheable for gs101 so we need to set the dma-coherent
property so the descriptors a
arm64: dts: exynos: gs101: ufs: add dma-coherent property
ufs-exynos driver configures the sysreg shareability as
cacheable for gs101 so we need to set the dma-coherent
property so the descriptors are also allocated cacheable.
This fixes the UFS stability issues we have seen with
the upstream UFS driver on gs101.
Fixes: 4c65d7054b4c ("arm64: dts: exynos: gs101: Add ufs and ufs-phy dt nodes")
Cc: stable@vger.kernel.org
Suggested-by: Will McVicker <willmcvicker@google.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Tested-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20250314-ufs-dma-coherent-v1-1-bdf9f9be2919@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 17a3657e | 24-May-2025 |
André Draszik <andre.draszik@linaro.org> |
arm64: dts: exynos: gs101: add dm-verity-device-corrupted syscon-reboot-mode
On gs101, the boot mode is stored both in a syscon register, and in
nvmem.
Add the dm-verity-device-corrupted reboot mod
arm64: dts: exynos: gs101: add dm-verity-device-corrupted syscon-reboot-mode
On gs101, the boot mode is stored both in a syscon register, and in
nvmem.
Add the dm-verity-device-corrupted reboot mode to the syscon-reboot-
based boot mode as well, as both (nvmem & syscon) modes should be in
sync.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20250524-b4-max77759-mfd-dts-v2-4-b479542eb97d@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 4292d182 | 24-May-2025 |
André Draszik <andre.draszik@linaro.org> |
arm64: dts: exynos: gs101-pixel-common: add nvmem-reboot-mode
Add the 'nvmem-reboot-mode' which is used to communicate a requested
boot mode to the boot loader.
Signed-off-by: André Draszik <andre.
arm64: dts: exynos: gs101-pixel-common: add nvmem-reboot-mode
Add the 'nvmem-reboot-mode' which is used to communicate a requested
boot mode to the boot loader.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20250524-b4-max77759-mfd-dts-v2-3-b479542eb97d@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 8deaddf1 | 24-May-2025 |
André Draszik <andre.draszik@linaro.org> |
arm64: dts: exynos: gs101-pixel-common: add Maxim MAX77759 PMIC
On Pixel 6 (and Pro), a MAX77759 companion PMIC for USB Type-C
applications is used, which contains four functional blocks (at
distinc
arm64: dts: exynos: gs101-pixel-common: add Maxim MAX77759 PMIC
On Pixel 6 (and Pro), a MAX77759 companion PMIC for USB Type-C
applications is used, which contains four functional blocks (at
distinct I2C addresses):
* top (including GPIO & NVMEM)
* charger
* fuel gauge
* TCPCi
This change adds the PMIC and the subnodes for the GPIO expander and
NVMEM, and defines the NVMEM layout.
The NVMEM layout is declared such that it matches downstream's
open-coded configuration [1].
Note:
The pinctrl nodes are kept sorted by the 'samsung,pins' property rather
than node name, as I think that makes it easier to look at and to add
new nodes unambiguously in the future. Its label is prefixed with 'if'
(for interface), because there are three PMICs in total in use on
Pixel 6 (Pro).
Link: https://android.googlesource.com/kernel/google-modules/bms/+/96e729a83817/max77759_maxq.c#67 [1]
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20250524-b4-max77759-mfd-dts-v2-2-b479542eb97d@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 73fd2bb6 | 19-Feb-2025 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: exynos: gs101: Change labels to lower-case
DTS coding style expects labels to be lowercase. No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).
Re
arm64: dts: exynos: gs101: Change labels to lower-case
DTS coding style expects labels to be lowercase. No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).
Reviewed-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20250219085726.70824-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| f64fdd3c | 07-Feb-2025 |
Tudor Ambarus <tudor.ambarus@linaro.org> |
arm64: dts: exynos: gs101: add ACPM protocol node
Add the ACPM protocol node. ACPM protocol provides interface for all
the client drivers making use of the features offered by the
Active Power Manag
arm64: dts: exynos: gs101: add ACPM protocol node
Add the ACPM protocol node. ACPM protocol provides interface for all
the client drivers making use of the features offered by the
Active Power Management (APM) module.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20250207-gs101-acpm-dt-v4-3-230ba8663a2d@linaro.org
[krzysztof: correct alphabetical node placement]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 23159ccf | 07-Feb-2025 |
Tudor Ambarus <tudor.ambarus@linaro.org> |
arm64: dts: exynos: gs101: add AP to APM mailbox node
GS101 has 14 mailbox controllers. Add the AP to APM mailbox node.
Mailbox controllers have a shared register that can be used for passing
the m
arm64: dts: exynos: gs101: add AP to APM mailbox node
GS101 has 14 mailbox controllers. Add the AP to APM mailbox node.
Mailbox controllers have a shared register that can be used for passing
the mailbox messages. The AP to APM mailbox controller is used just as a
doorbell mechanism. It raises interrupt to the firmware after the mailbox
message has been written to SRAM where the TX/RX rings are defined.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20250207-gs101-acpm-dt-v4-2-230ba8663a2d@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 48e7821b | 07-Feb-2025 |
Tudor Ambarus <tudor.ambarus@linaro.org> |
arm64: dts: exynos: gs101: add SRAM node
SRAM is used by the ACPM protocol to retrieve the ACPM channels
information, which includes the TX/RX rings among other channel
configuration data. Add the S
arm64: dts: exynos: gs101: add SRAM node
SRAM is used by the ACPM protocol to retrieve the ACPM channels
information, which includes the TX/RX rings among other channel
configuration data. Add the SRAM node.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20250207-gs101-acpm-dt-v4-1-230ba8663a2d@linaro.org
[krzysztof: correct alphabetical node placement]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| ae32b65c | 10-Feb-2025 |
André Draszik <andre.draszik@linaro.org> |
arm64: dts: exynos: gs101: add reboot-mode support (SYSIP_DAT0)
syscon-reboot-mode can be used to indicate the reboot mode for the
bootloader.
While not sufficient for all boot modes, the boot load
arm64: dts: exynos: gs101: add reboot-mode support (SYSIP_DAT0)
syscon-reboot-mode can be used to indicate the reboot mode for the
bootloader.
While not sufficient for all boot modes, the boot loader does use
SYSIP_DAT0 (PMU + 0x0810) to determine some of the actions it should
take. This change helps it deciding what to do in those cases.
For complete support, we'll also have to write the boot mode to an
NVMEM storage location, but we have no upstream driver for that yet.
Nevertheless, this patch is a step towards full support for the boot
mode.
Note1: Android also uses 'shutdown,thermal' and
shutdown,thermal,battery', but that can not be described in DT as ','
is used to denote vendor prefixes. I've left them out from here for
that reason.
Note2: downstream / bootloader recognizes one more mode: 'dm-verity
device corrupted' with value 0x50, but we can not describe that in DT
using a property name due to the space, so it's been left out from here
as well. This string appears to come from drivers/md/dm-verity-target.c
and should probably be changed there in a follow-up patch, so that it
can be used in reboot-mode nodes like this one here.
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20250210-gs101-renppt-dts-v2-3-fb33fda6fc4b@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 6572a93a | 10-Feb-2025 |
André Draszik <andre.draszik@linaro.org> |
arm64: dts: exynos: gs101: align poweroff writes with downstream
For power off, downstream only clears bit 8 and leaves all other bits
untouched, whereas this here ends up setting bit 8 and clearing
arm64: dts: exynos: gs101: align poweroff writes with downstream
For power off, downstream only clears bit 8 and leaves all other bits
untouched, whereas this here ends up setting bit 8 and clearing all
others, due to how sysconf-poweroff parses the DT.
I noticed this discrepancy while debugging some reboot related
differences between up- and downstream and it's useful to align the
behaviour here.
Note: for reboot downstream seems to be incorrectly writing 0x00000002
and not just setting bit 1 (which is the only R/W bit in this
register), so we keep that one as-is here.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20250210-gs101-renppt-dts-v2-2-fb33fda6fc4b@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 825c4bfd | 17-Jan-2025 |
André Draszik <andre.draszik@linaro.org> |
arm64: dts: exynos: gs101-raven: add new board file
Raven is Google's code name for Pixel 6 Pro. Similar to Pixel 6
(Oriole), this is also based around its Tensor gs101 SoC.
For now, the relevant d
arm64: dts: exynos: gs101-raven: add new board file
Raven is Google's code name for Pixel 6 Pro. Similar to Pixel 6
(Oriole), this is also based around its Tensor gs101 SoC.
For now, the relevant difference here is the display resolution:
1440 x 3120 instead of 1080 x 2400.
Create a new board file to reflect this difference.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20250117-gs101-simplefb-v4-4-a5b90ca2f917@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 58dbafb7 | 17-Jan-2025 |
André Draszik <andre.draszik@linaro.org> |
arm64: dts: exynos: gs101-oriole: move common Pixel6 & 6Pro parts into a .dtsi
In order to support Pixel 6 (Oriole), Pixel 6 Pro (Raven), Pixel 6a
(Bluejay), and all other versions correctly, we hav
arm64: dts: exynos: gs101-oriole: move common Pixel6 & 6Pro parts into a .dtsi
In order to support Pixel 6 (Oriole), Pixel 6 Pro (Raven), Pixel 6a
(Bluejay), and all other versions correctly, we have to be able to
distinguish them properly as we add support for more features.
For example, Raven has a larger display. There are other differences,
like battery design capacity, etc.
Move all the parts that are common for now into a
gs101-pixel-common.dtsi, and just leave the display related things in
gs101-oriole.dts.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20250117-gs101-simplefb-v4-3-a5b90ca2f917@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| befbb62c | 17-Jan-2025 |
André Draszik <andre.draszik@linaro.org> |
arm64: dts: exynos: gs101-oriole: configure simple-framebuffer
The bootloader configures the display hardware for a framebuffer at the
given address, let's add a simple-framebuffer node here until w
arm64: dts: exynos: gs101-oriole: configure simple-framebuffer
The bootloader configures the display hardware for a framebuffer at the
given address, let's add a simple-framebuffer node here until we get a
proper DRM driver.
This has several benefits since it's an OLED display:
* energy consumption goes down significantly, as it changes from white
(as left by bootloader) to black (linux console), and we generally
don't run out of battery anymore when plugged into a USB port
* less of a burn-in effect I assume
* phone stays cooler due to reduced energy consumption by display
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20250117-gs101-simplefb-v4-2-a5b90ca2f917@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 817473b6 | 03-Dec-2024 |
André Draszik <andre.draszik@linaro.org> |
arm64: dts: exynos: gs101-oriole: add pd-disable and typec-power-opmode
When the serial console is enabled, we need to disable power delivery
since serial uses the SBU1/2 pins and appears to confuse
arm64: dts: exynos: gs101-oriole: add pd-disable and typec-power-opmode
When the serial console is enabled, we need to disable power delivery
since serial uses the SBU1/2 pins and appears to confuse the TCPCI,
resulting in endless interrupts.
For now, change the DT such that the serial console continues working.
Note1: We can not have both typec-power-opmode and
new-source-frs-typec-current active at the same time, as otherwise DT
binding checks complain.
Note2: When using a downstream DT, the Pixel boot-loader will modify
the DT accordingly before boot, but for this upstream DT it doesn't
know where to find the TCPCI node. The intention is for this commit to
be reverted once an updated Pixel boot-loader becomes available.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-5-1412783a6b01@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| ddbf40d8 | 03-Dec-2024 |
André Draszik <andre.draszik@linaro.org> |
arm64: dts: exynos: gs101-oriole: enable Maxim max77759 TCPCi
On Pixel 6 (and Pro), a max77759 companion PMIC for USB Type-C
applications is used, which contains four functional blocks (at
distinct
arm64: dts: exynos: gs101-oriole: enable Maxim max77759 TCPCi
On Pixel 6 (and Pro), a max77759 companion PMIC for USB Type-C
applications is used, which contains four functional blocks (at
distinct I2C addresses):
* top (including GPIO)
* charger
* fuel gauge
* TCPCi
While in the same package, TCPCi and Fuel Gauge have separate I2C
addresses, interrupt lines and interrupt status registers and can be
treated independently.
The TCPCi is required to detect and handle connector orientation in
Pixel's USB PHY driver, and to configure the USB controller's role
(host vs device).
This change adds the TCPCi part as it can be independent and doesn't
need a top-level MFD.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-4-1412783a6b01@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| 95350c0e | 03-Dec-2024 |
André Draszik <andre.draszik@linaro.org> |
arm64: dts: exynos: gs101: allow stable USB phy Vbus detection
For the DWC3 core to reliably detect the connected phy's Vbus state, we
need to disable phy suspend.
Add
snps,dis_u2_susphy_quirk
arm64: dts: exynos: gs101: allow stable USB phy Vbus detection
For the DWC3 core to reliably detect the connected phy's Vbus state, we
need to disable phy suspend.
Add
snps,dis_u2_susphy_quirk
snps,dis_u3_susphy_quirk
to do that.
While at it, also add
snps,has-lpm-erratum
as this is set downstream which implies that the core was configured
with LPM Erratum. We should do the same here.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-3-1412783a6b01@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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