| c5dca386 | 15-Sep-2025 |
Fabio M. De Francesco <fabio.m.de.francesco@linux.intel.com> |
cxl: Documentation/driver-api/cxl: Describe the x86 Low Memory Hole solution
Add documentation on how to resolve conflicts between CXL Fixed Memory Windows, Platform Low Memory Holes, intermediate S
cxl: Documentation/driver-api/cxl: Describe the x86 Low Memory Hole solution
Add documentation on how to resolve conflicts between CXL Fixed Memory Windows, Platform Low Memory Holes, intermediate Switch and Endpoint Decoders.
[dj]: Fixed inconsistent spacing after '.' [dj]: Fixed subject line from Alison. [dj]: Removed '::' before table from Bagas.
Reviewed-by: Gregory Price <gourry@gourry.net> Signed-off-by: Fabio M. De Francesco <fabio.m.de.francesco@linux.intel.com> Reviewed-by: Bagas Sanjaya <bagasdotme@gmail.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| a4144081 | 18-Aug-2025 |
Rakuram Eswaran <rakuram.e96@gmail.com> |
Documentation/driver-api: Fix typo error in cxl
Fixed the following typo errors
intersparsed ==> interspersed in Documentation/driver-api/cxl/platform/bios-and-efi.rst
Reviewed-by: Jonathan Camero
Documentation/driver-api: Fix typo error in cxl
Fixed the following typo errors
intersparsed ==> interspersed in Documentation/driver-api/cxl/platform/bios-and-efi.rst
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250818175335.5312-1-rakuram.e96@gmail.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| 8ad85794 | 16-Jun-2025 |
Alok Tiwari <alok.a.tiwari@oracle.com> |
cxl: docs/devices Fix typos and clarify wording in device-types.rst
Fix several typos and improve comment clarity in the CXL device types docs: "w/" replaced with "with" "sill" -> "still" "The al
cxl: docs/devices Fix typos and clarify wording in device-types.rst
Fix several typos and improve comment clarity in the CXL device types docs: "w/" replaced with "with" "sill" -> "still" "The allows" -> "This allows" "capacity" corrected to "capable" "more devices" corrected to "more upstream devices" in MLD description
These changes improve readability and enhance the documentation quality.
[ dj: Fix up "one or more hosts" to "one or more upstream devices" from Gregory ]
Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com> Reviewed-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250616060737.1645393-1-alok.a.tiwari@oracle.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| 7d14230d | 10-Jun-2025 |
Nai-Chen Cheng <bleach1827@gmail.com> |
Documentation: fix typo in CXL driver documentation
Fix typo 'enumates' to 'enumerate' in CXL driver operation documentation to improve readability.
Signed-off-by: Nai-Chen Cheng <bleach1827@gmail.
Documentation: fix typo in CXL driver documentation
Fix typo 'enumates' to 'enumerate' in CXL driver operation documentation to improve readability.
Signed-off-by: Nai-Chen Cheng <bleach1827@gmail.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Li Ming <ming.li@zohomail.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250610173152.33566-1-bleach1827@gmail.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| 5af29a58 | 09-Jun-2025 |
Alok Tiwari <alok.a.tiwari@oracle.com> |
Documentation: cxl: fix typos and improve clarity in memory-devices.rst
This patch corrects several typographical issues and improves phrasing in memory-devices.rst:
- Fixes duplicate word ("1 one"
Documentation: cxl: fix typos and improve clarity in memory-devices.rst
This patch corrects several typographical issues and improves phrasing in memory-devices.rst:
- Fixes duplicate word ("1 one") and adjusts phrasing for clarity. - Adds missing hyphen in "on-device". - Corrects "a give memory device" to "a given memory device". - fix singular/plural "decoder resource" -> "decoder resources". - Clarifies "spans to Host Bridges" -> "spans two Host Bridges". - change "at a" -> "a"
These changes improve readability and accuracy of the documentation.
Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Link: https://patch.msgid.link/20250609171130.2375901-1-alok.a.tiwari@oracle.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| fc785615 | 15-May-2025 |
Dave Jiang <dave.jiang@intel.com> |
cxl: doc/linux/access-coordinates Update access coordinates calculation methods
Add documentation on how to calculate the access coordinates for a given CXL region in detail.
Reviewed-by: Gregory P
cxl: doc/linux/access-coordinates Update access coordinates calculation methods
Add documentation on how to calculate the access coordinates for a given CXL region in detail.
Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20250515000923.2590820-4-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| 1ce91b37 | 15-May-2025 |
Dave Jiang <dave.jiang@intel.com> |
cxl: docs/platform/acpi/srat Add generic target documentation
Add description in the SRAT document to describe the Generic Port Affinity sub-table.
Reviewed-by: Gregory Price <gourry@gourry.net> Re
cxl: docs/platform/acpi/srat Add generic target documentation
Add description in the SRAT document to describe the Generic Port Affinity sub-table.
Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20250515000923.2590820-3-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| 49cee8fe | 15-May-2025 |
Dave Jiang <dave.jiang@intel.com> |
cxl: docs/platform/cdat reference documentation
Add documentation for CDAT structures for CXL usages.
Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Alison Schofield <alison.schofield@
cxl: docs/platform/cdat reference documentation
Add documentation for CDAT structures for CXL usages.
Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20250515000923.2590820-2-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| f97bdc61 | 12-May-2025 |
Alison Schofield <alison.schofield@intel.com> |
Documentation: Update the CXL Maturity Map
Changes for extended-linear cache, hetero-interleave, and HPA->DPA address translation.
Signed-off-by: Alison Schofield <alison.schofield@intel.com> Revie
Documentation: Update the CXL Maturity Map
Changes for extended-linear cache, hetero-interleave, and HPA->DPA address translation.
Signed-off-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512214225.1389484-1-alison.schofield@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| df63e012 | 12-May-2025 |
Gregory Price <gourry@gourry.net> |
cxl: docs/allocation/hugepages
Add docs on how CXL capacity interacts with CMA and HugeTLB allocation interfaces.
Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/202
cxl: docs/allocation/hugepages
Add docs on how CXL capacity interacts with CMA and HugeTLB allocation interfaces.
Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-17-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| f109e77d | 12-May-2025 |
Gregory Price <gourry@gourry.net> |
cxl: docs/allocation/reclaim
Document a bit about how reclaim interacts with various CXL configurations.
Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/202505121621
cxl: docs/allocation/reclaim
Document a bit about how reclaim interacts with various CXL configurations.
Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-16-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| 419dc40b | 12-May-2025 |
Gregory Price <gourry@gourry.net> |
cxl: docs/allocation/page-allocator
Document some interesting interactions that occur when exposing CXL memory capacity to page allocator.
Signed-off-by: Gregory Price <gourry@gourry.net> Link: htt
cxl: docs/allocation/page-allocator
Document some interesting interactions that occur when exposing CXL memory capacity to page allocator.
Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-15-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| 78ab6751 | 12-May-2025 |
Gregory Price <gourry@gourry.net> |
cxl: docs/allocation/dax
Small example of accessing CXL memory capacity via DAX device
Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-14-gour
cxl: docs/allocation/dax
Small example of accessing CXL memory capacity via DAX device
Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-14-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| 641fdea6 | 12-May-2025 |
Gregory Price <gourry@gourry.net> |
cxl: docs/linux/memory-hotplug
Add documentation on how the CXL driver surfaces memory through the DAX driver and memory-hotplug.
Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patc
cxl: docs/linux/memory-hotplug
Add documentation on how the CXL driver surfaces memory through the DAX driver and memory-hotplug.
Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-13-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| 36e9f71b | 12-May-2025 |
Gregory Price <gourry@gourry.net> |
cxl: docs/linux/dax-driver documentation
Add documentation on how the CXL driver interacts with the DAX driver.
Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250
cxl: docs/linux/dax-driver documentation
Add documentation on how the CXL driver interacts with the DAX driver.
Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-12-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| 2e2865a1 | 12-May-2025 |
Gregory Price <gourry@gourry.net> |
cxl: docs/linux - add cxl-driver theory of operation
Add docs for the CXL driver that explains the base devices, decoder types, region types, mailbox interfaces, and decoder programming.
Signed-off
cxl: docs/linux - add cxl-driver theory of operation
Add docs for the CXL driver that explains the base devices, decoder types, region types, mailbox interfaces, and decoder programming.
Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-10-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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| bef826ea | 12-May-2025 |
Gregory Price <gourry@gourry.net> |
cxl: docs/linux - early boot configuration
Document __init time configurations that affect CXL driver probe process and memory region configuration.
Signed-off-by: Gregory Price <gourry@gourry.net>
cxl: docs/linux - early boot configuration
Document __init time configurations that affect CXL driver probe process and memory region configuration.
Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512162134.3596150-9-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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