| 5cd2a743 | 05-Jan-2026 |
Pankaj Patil <pankaj.patil@oss.qualcomm.com> |
dt-bindings: cache: qcom,llcc: Remove duplicate llcc7_base for Glymur
Drop redundant llcc7_base entry from Glymur LLCC reg-items
Fixes: bd0b8028ce5f ("dt-bindings: cache: qcom,llcc: Document Glymur
dt-bindings: cache: qcom,llcc: Remove duplicate llcc7_base for Glymur
Drop redundant llcc7_base entry from Glymur LLCC reg-items
Fixes: bd0b8028ce5f ("dt-bindings: cache: qcom,llcc: Document Glymur LLCC block")
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260105130050.1062903-1-pankaj.patil@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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| d52341da | 17-Nov-2025 |
Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> |
dt-bindings: cache: sifive,ccache0: add a pic64gx compatible
The pic64gx use the same IP than mpfs, therefore add compatibility with
mpfs as fallback.
Signed-off-by: Pierre-Henry Moussay <pierre-he
dt-bindings: cache: sifive,ccache0: add a pic64gx compatible
The pic64gx use the same IP than mpfs, therefore add compatibility with
mpfs as fallback.
Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 51b081cd | 14-May-2025 |
Ben Zong-You Xie <ben717@andestech.com> |
dt-bindings: cache: add QiLai compatible to ax45mp
Add a new compatible string for ax45mp-cache on QiLai SoC.
Also, add allOf constraints to enforce specific cache-sets and cache-size
values for qi
dt-bindings: cache: add QiLai compatible to ax45mp
Add a new compatible string for ax45mp-cache on QiLai SoC.
Also, add allOf constraints to enforce specific cache-sets and cache-size
values for qilai-ax45mp-cache.
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 64d60a02 | 13-May-2025 |
Rob Herring (Arm) <robh@kernel.org> |
dt-bindings: cache: Convert marvell,tauros2-cache to DT schema
Convert the Marvell Tauros2 Cache binding to DT schema.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Andrew Lunn <a
dt-bindings: cache: Convert marvell,tauros2-cache to DT schema
Convert the Marvell Tauros2 Cache binding to DT schema.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| 438d216e | 13-May-2025 |
Rob Herring (Arm) <robh@kernel.org> |
dt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schema
Convert the Marvell Feroceon/Kirkwood Cache binding to DT schema format.
Use "marvell,kirkwood-cache" for the filename ins
dt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schema
Convert the Marvell Feroceon/Kirkwood Cache binding to DT schema format.
Use "marvell,kirkwood-cache" for the filename instead as that's only
compatible used in a .dts upstream.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| d58a73c9 | 12-May-2025 |
Conor Dooley <conor.dooley@microchip.com> |
dt-bindings: cache: add specific RZ/Five compatible to ax45mp
When the binding was originally written, it was assumed that all
ax45mp-caches had the same properties etc. This has turned out to be
in
dt-bindings: cache: add specific RZ/Five compatible to ax45mp
When the binding was originally written, it was assumed that all
ax45mp-caches had the same properties etc. This has turned out to be
incorrect, as the QiLai SoC has a different number of cache-sets.
Add a specific compatible for the RZ/Five for property enforcement and
in case there turns out to be additional differences between these
implementations of the cache controller.
Acked-by: Ben Zong-You Xie <ben717@andestech.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| a83e18ca | 31-Oct-2024 |
Jingyi Wang <quic_jingyw@quicinc.com> |
dt-bindings: cache: qcom,llcc: Document the QCS8300 LLCC
Document the Last Level Cache Controller on QCS8300 platform.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-b
dt-bindings: cache: qcom,llcc: Document the QCS8300 LLCC
Document the Last Level Cache Controller on QCS8300 platform.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Link: https://lore.kernel.org/r/20241031-qcs8300_llcc-v3-1-bb56952cb83b@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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| 08e2d7c6 | 10-Oct-2024 |
Song Xue <quic_songxue@quicinc.com> |
dt-bindings: cache: qcom,llcc: Document the QCS615 LLCC
Document the LLCC on the QCS615 platform.
The QCS615 platform has LLCC as the system cache controller. It
includes 1 LLCC instance and 1 broa
dt-bindings: cache: qcom,llcc: Document the QCS615 LLCC
Document the LLCC on the QCS615 platform.
The QCS615 platform has LLCC as the system cache controller. It
includes 1 LLCC instance and 1 broadcast interface.
Signed-off-by: Song Xue <quic_songxue@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241010-add_llcc_support_for_qcs615-v2-1-044432450a75@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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| c190f390 | 31-May-2024 |
Unnathi Chalicheemala <quic_uchalich@quicinc.com> |
dt-bindings: arm: msm: Add llcc Broadcast_AND register
The LLCC block in SM8450, SM8550 and SM8650 have a new register
space for Broadcast_AND region. This is used to check that all
channels have bi
dt-bindings: arm: msm: Add llcc Broadcast_AND register
The LLCC block in SM8450, SM8550 and SM8650 have a new register
space for Broadcast_AND region. This is used to check that all
channels have bit set to "1", mainly in SCID activation/deactivation.
Previously we were mapping only the Broadcast_OR region assuming
there was only one broadcast register region. Now we also map
Broadcast_AND region.
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/3306bf3026f38b0486e00307d26827d71c99915d.1717014052.git.quic_uchalich@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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