3b051bb7 | 10-Dec-2024 |
Yicong Yang <yangyicong@hisilicon.com> |
drivers/perf: hisi: Export associated CPUs of each PMU through sysfs
Although the event of the uncore PMU can only be opened on a single CPU, some PMU does have the affinity on a range of CPUs. For
drivers/perf: hisi: Export associated CPUs of each PMU through sysfs
Although the event of the uncore PMU can only be opened on a single CPU, some PMU does have the affinity on a range of CPUs. For example the L3C PMU is associated to the CPUs sharing the L3T it monitors. Users may infer this affinity by the PMU name which may have SCCL ID and CCL ID encoded (for L3C etc), but it's not that straightforward. So export this information by adding an "associated_cpus" sysfs attribute then user can get this directly.
Reviewed-by: Jonathan Cameron <Joanthan.Cameron@huawei.com> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Link: https://lore.kernel.org/r/20241210141525.37788-9-yangyicong@huawei.com Signed-off-by: Will Deacon <will@kernel.org>
show more ...
|
5fcccba1 | 08-Nov-2024 |
Gowthami Thiagarajan <gthiagarajan@marvell.com> |
perf/marvell: Odyssey LLC-TAD performance monitor support
Each TAD provides eight 64-bit counters for monitoring cache behavior.The driver always configures the same counter for all the TADs. The us
perf/marvell: Odyssey LLC-TAD performance monitor support
Each TAD provides eight 64-bit counters for monitoring cache behavior.The driver always configures the same counter for all the TADs. The user would end up effectively reserving one of eight counters in every TAD to look across all TADs. The occurrences of events are aggregated and presented to the user at the end of running the workload. The driver does not provide a way for the user to partition TADs so that different TADs are used for different applications.
The performance events reflect various internal or interface activities. By combining the values from multiple performance counters, cache performance can be measured in terms such as: cache miss rate, cache allocations, interface retry rate, internal resource occupancy, etc.
Each supported counter's event and formatting information is exposed to sysfs at /sys/devices/tad/. Use perf tool stat command to measure the pmu events. For instance:
perf stat -e tad_hit_ltg,tad_hit_dtg <workload>
Signed-off-by: Gowthami Thiagarajan <gthiagarajan@marvell.com> Link: https://lore.kernel.org/r/20241108040619.753343-6-gthiagarajan@marvell.com Signed-off-by: Will Deacon <will@kernel.org>
show more ...
|
d950c381 | 08-Nov-2024 |
Gowthami Thiagarajan <gthiagarajan@marvell.com> |
perf/marvell: Odyssey DDR Performance monitor support
Odyssey DRAM Subsystem supports eight counters for monitoring performance and software can program those counters to monitor any of the defined
perf/marvell: Odyssey DDR Performance monitor support
Odyssey DRAM Subsystem supports eight counters for monitoring performance and software can program those counters to monitor any of the defined performance events. Supported performance events include those counted at the interface between the DDR controller and the PHY, interface between the DDR Controller and the CHI interconnect, or within the DDR Controller.
Additionally DSS also supports two fixed performance event counters, one for ddr reads and the other for ddr writes.
Signed-off-by: Gowthami Thiagarajan <gthiagarajan@marvell.com> Link: https://lore.kernel.org/r/20241108040619.753343-4-gthiagarajan@marvell.com Signed-off-by: Will Deacon <will@kernel.org>
show more ...
|
8632306e | 05-Dec-2024 |
Ilkka Koskinen <ilkka@os.amperecomputing.com> |
Documentation: dwc_pcie_pmu: Fix the mnemonics and eventid
Fix the event id and type in the example. In addition, the recent fix, which addressed the mnemonics with mixed case, didn't fix the docume
Documentation: dwc_pcie_pmu: Fix the mnemonics and eventid
Fix the event id and type in the example. In addition, the recent fix, which addressed the mnemonics with mixed case, didn't fix the document. Match the names with the driver.
Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Reviewed-by: Shuai Xue <xueshuai@linux.alibaba.com> Link: https://lore.kernel.org/r/20241205061914.5568-3-ilkka@os.amperecomputing.com Signed-off-by: Will Deacon <will@kernel.org>
show more ...
|
bce61d5c | 31-Oct-2024 |
Besar Wicaksono <bwicaksono@nvidia.com> |
perf: arm_cspmu: nvidia: monitor all ports by default
Some NVIDIA PMUs like the NVLINK-C2C, CNVLINK, and PCIE PMU provide port filtering. If the port filter is set to zero, the counter of these PMUs
perf: arm_cspmu: nvidia: monitor all ports by default
Some NVIDIA PMUs like the NVLINK-C2C, CNVLINK, and PCIE PMU provide port filtering. If the port filter is set to zero, the counter of these PMUs will not capture any event. To avoid meaningless experiment, the driver sets the port filter value to a default non-zero value.
Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com> Link: https://lore.kernel.org/r/20241031142118.1865965-5-bwicaksono@nvidia.com Signed-off-by: Will Deacon <will@kernel.org>
show more ...
|
ca26df4b | 31-Oct-2024 |
Besar Wicaksono <bwicaksono@nvidia.com> |
perf: arm_cspmu: nvidia: enable NVLINK-C2C port filtering
Enable NVLINK-C2C port filtering to distinguish traffic from different GPUs connected to NVLINK-C2C.
Signed-off-by: Besar Wicaksono <bwicak
perf: arm_cspmu: nvidia: enable NVLINK-C2C port filtering
Enable NVLINK-C2C port filtering to distinguish traffic from different GPUs connected to NVLINK-C2C.
Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com> Link: https://lore.kernel.org/r/20241031142118.1865965-4-bwicaksono@nvidia.com Signed-off-by: Will Deacon <will@kernel.org>
show more ...
|
4d5a7680 | 04-Sep-2024 |
Robin Murphy <robin.murphy@arm.com> |
perf: Add driver for Arm NI-700 interconnect PMU
The Arm NI-700 Network-on-Chip Interconnect has a relatively straightforward design with a hierarchy of voltage, power, and clock domains, where each
perf: Add driver for Arm NI-700 interconnect PMU
The Arm NI-700 Network-on-Chip Interconnect has a relatively straightforward design with a hierarchy of voltage, power, and clock domains, where each clock domain then contains a number of interface units and a PMU which can monitor events thereon. As such, it begets a relatively straightforward driver to interface those PMUs with perf.
Even more so than with arm-cmn, users will require detailed knowledge of the wider system topology in order to meaningfully analyse anything, since the interconnect itself cannot know what lies beyond the boundary of each inscrutably-numbered interface. Given that, for now they are also expected to refer to the NI-700 documentation for the relevant event IDs to provide as well. An identifier is implemented so we can come back and add jevents if anyone really wants to.
Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/9933058d0ab8138c78a61cd6852ea5d5ff48e393.1725470837.git.robin.murphy@arm.com Signed-off-by: Will Deacon <will@kernel.org>
show more ...
|
d1c93d5c | 29-Aug-2024 |
Yicong Yang <yangyicong@hisilicon.com> |
drivers/perf: hisi_pcie: Export supported Root Ports [bdf_min, bdf_max]
Currently users can get the Root Ports supported by the PCIe PMU by "bus" sysfs attributes which indicates the PCIe bus number
drivers/perf: hisi_pcie: Export supported Root Ports [bdf_min, bdf_max]
Currently users can get the Root Ports supported by the PCIe PMU by "bus" sysfs attributes which indicates the PCIe bus number where Root Ports are located. This maybe insufficient since Root Ports supported by different PCIe PMUs may be located on the same PCIe bus. So export the BDF range the Root Ports additionally.
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20240829090332.28756-4-yangyicong@huawei.com Signed-off-by: Will Deacon <will@kernel.org>
show more ...
|
90b4a1a9 | 12-Apr-2024 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> |
Documentation: thunderx2-pmu: Use /sys/bus/event_source/devices paths
To allow setting an appropriate parent for the struct pmu device remove existing references to /sys/devices/ path.
Signed-off-b
Documentation: thunderx2-pmu: Use /sys/bus/event_source/devices paths
To allow setting an appropriate parent for the struct pmu device remove existing references to /sys/devices/ path.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20240412161057.14099-11-Jonathan.Cameron@huawei.com Signed-off-by: Will Deacon <will@kernel.org>
show more ...
|
eff6af53 | 12-Apr-2024 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> |
Documentation: hns-pmu: Use /sys/bus/event_source/devices paths
To allow setting an appropriate parent for the struct pmu device remove existing references to /sys/devices/ path.
Reviewed-by: Greg
Documentation: hns-pmu: Use /sys/bus/event_source/devices paths
To allow setting an appropriate parent for the struct pmu device remove existing references to /sys/devices/ path.
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20240412161057.14099-5-Jonathan.Cameron@huawei.com Signed-off-by: Will Deacon <will@kernel.org>
show more ...
|
b037e40a | 05-Mar-2024 |
Yicong Yang <yangyicong@hisilicon.com> |
docs: perf: Fix build warning of hisi-pcie-pmu.rst
`make htmldocs SPHINXDIRS="admin-guide"` shows below warnings: Documentation/admin-guide/perf/hisi-pcie-pmu.rst:48: ERROR: Unexpected indentation.
docs: perf: Fix build warning of hisi-pcie-pmu.rst
`make htmldocs SPHINXDIRS="admin-guide"` shows below warnings: Documentation/admin-guide/perf/hisi-pcie-pmu.rst:48: ERROR: Unexpected indentation. Documentation/admin-guide/perf/hisi-pcie-pmu.rst:49: WARNING: Block quote ends without a blank line; unexpected unindent.
Fix this.
Closes: https://lore.kernel.org/lkml/20231011172250.5a6498e5@canb.auug.org.au/ Fixes: 89a032923d4b ("docs: perf: Update usage for target filter of hisi-pcie-pmu") Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Link: https://lore.kernel.org/r/20240305122517.12179-1-yangyicong@huawei.com Signed-off-by: Will Deacon <will@kernel.org>
show more ...
|
0abe7f61 | 12-Oct-2023 |
Ilkka Koskinen <ilkka@os.amperecomputing.com> |
docs/perf: Add ampere_cspmu to toctree to fix a build warning
Add ampere_cspmu to toctree in order to address the following warning produced when building documents:
Documentation/admin-guide/perf
docs/perf: Add ampere_cspmu to toctree to fix a build warning
Add ampere_cspmu to toctree in order to address the following warning produced when building documents:
Documentation/admin-guide/perf/ampere_cspmu.rst: WARNING: document isn't included in any toctree
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Closes: https://lore.kernel.org/all/20231011172250.5a6498e5@canb.auug.org.au/ Fixes: 53a810ad3c5c ("perf: arm_cspmu: ampere_cspmu: Add support for Ampere SoC PMU") Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Link: https://lore.kernel.org/r/20231012074103.3772114-1-ilkka@os.amperecomputing.com Signed-off-by: Will Deacon <will@kernel.org>
show more ...
|