hwpmc: add MPERF/APERF MSR support for AMD/Intel CPUs

Add support for reading the MPERF (MSR 0xE7) and APERF (MSR 0xE8)
model-specific registers on AMD/Intel CPUs through hwpmc(4). These
counters tr

hwpmc: add MPERF/APERF MSR support for AMD/Intel CPUs

Add support for reading the MPERF (MSR 0xE7) and APERF (MSR 0xE8)
model-specific registers on AMD/Intel CPUs through hwpmc(4). These
counters track maximum and actual performance frequency respectively,
and are used to compute effective CPU frequency scaling independent
of the nominal TSC rate. The name of the class was chosen as PERF
because later support for other PERF MSRs can be added to the same
class.

Extend libpmc(3) to expose the AMD/Intel MPERF/APERF counters added
to hwpmc(4) in the companion kernel change, so userland consumers
(pmcstat(8), etc.) can allocate and read these events by name.

Document the new PERF class and its MPERF/APERF counters in a new
pmc.perf.3 manual page, describing their semantics and how to read
them via pmc(3) and pmcstat(8).

Bump PMC_VERSION_MINOR.

Signed-off-by: Anderson Nascimento <anascime@amd.com>
Reviewed by: Ali Mashtizadeh <ali@mashtizadeh.com>, mhorne
Reviewed by: ziaee (manpages)
Sponsored by: AMD
Differential Revision: https://reviews.freebsd.org/D58647

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