| acp.h (61c80c77b4f35e229347551d13e265752f067151) | acp.h (490be7ba2a018093fbfa6c2dd80d7d0c190c4c98) |
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| 1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2/* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7 * 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> --- 15 unchanged lines hidden (view full) --- 24#define ACP_REG_POLL_INTERVAL 500 25#define ACP_REG_POLL_TIMEOUT_US 2000 26#define ACP_DMA_COMPLETE_TIMEOUT_US 5000 27 28#define ACP3X_PGFSM_CNTL_POWER_ON_MASK 0x01 29#define ACP3X_PGFSM_STATUS_MASK 0x03 30#define ACP6X_PGFSM_CNTL_POWER_ON_MASK 0x07 31#define ACP6X_PGFSM_STATUS_MASK 0x0F | 1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2/* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7 * 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> --- 15 unchanged lines hidden (view full) --- 24#define ACP_REG_POLL_INTERVAL 500 25#define ACP_REG_POLL_TIMEOUT_US 2000 26#define ACP_DMA_COMPLETE_TIMEOUT_US 5000 27 28#define ACP3X_PGFSM_CNTL_POWER_ON_MASK 0x01 29#define ACP3X_PGFSM_STATUS_MASK 0x03 30#define ACP6X_PGFSM_CNTL_POWER_ON_MASK 0x07 31#define ACP6X_PGFSM_STATUS_MASK 0x0F |
| 32#define ACP70_PGFSM_CNTL_POWER_ON_MASK 0x1F 33#define ACP70_PGFSM_STATUS_MASK 0xFF |
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| 32 33#define ACP_POWERED_ON 0x00 34#define ACP_ASSERT_RESET 0x01 35#define ACP_RELEASE_RESET 0x00 36#define ACP_SOFT_RESET_DONE_MASK 0x00010001 37#define ACP_DSP_ASSERT_RESET 0x04 38#define ACP_DSP_RELEASE_RESET 0x00 39#define ACP_DSP_SOFT_RESET_DONE_MASK 0x00050004 40 41#define ACP_DSP_INTR_EN_MASK 0x00000001 42#define ACP3X_SRAM_PTE_OFFSET 0x02050000 43#define ACP5X_SRAM_PTE_OFFSET 0x02050000 44#define ACP6X_SRAM_PTE_OFFSET 0x03800000 | 34 35#define ACP_POWERED_ON 0x00 36#define ACP_ASSERT_RESET 0x01 37#define ACP_RELEASE_RESET 0x00 38#define ACP_SOFT_RESET_DONE_MASK 0x00010001 39#define ACP_DSP_ASSERT_RESET 0x04 40#define ACP_DSP_RELEASE_RESET 0x00 41#define ACP_DSP_SOFT_RESET_DONE_MASK 0x00050004 42 43#define ACP_DSP_INTR_EN_MASK 0x00000001 44#define ACP3X_SRAM_PTE_OFFSET 0x02050000 45#define ACP5X_SRAM_PTE_OFFSET 0x02050000 46#define ACP6X_SRAM_PTE_OFFSET 0x03800000 |
| 47#define ACP70_SRAM_PTE_OFFSET ACP6X_SRAM_PTE_OFFSET |
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| 45#define PAGE_SIZE_4K_ENABLE 0x2 46#define ACP_PAGE_SIZE 0x1000 47#define ACP_DMA_CH_RUN 0x02 48#define ACP_MAX_DESC_CNT 0x02 49#define DSP_FW_RUN_ENABLE 0x01 50#define ACP_SHA_RUN 0x01 51#define ACP_SHA_RESET 0x02 52#define ACP_SHA_HEADER 0x01 --- 5 unchanged lines hidden (view full) --- 58 59#define ACP_DEFAULT_DRAM_LENGTH 0x00080000 60#define ACP3X_SCRATCH_MEMORY_ADDRESS 0x02050000 61#define ACP_SYSTEM_MEMORY_WINDOW 0x4000000 62#define ACP_IRAM_BASE_ADDRESS 0x000000 63#define ACP_DRAM_BASE_ADDRESS 0x01000000 64#define ACP_DRAM_PAGE_COUNT 128 65#define ACP_SRAM_BASE_ADDRESS 0x3806000 | 48#define PAGE_SIZE_4K_ENABLE 0x2 49#define ACP_PAGE_SIZE 0x1000 50#define ACP_DMA_CH_RUN 0x02 51#define ACP_MAX_DESC_CNT 0x02 52#define DSP_FW_RUN_ENABLE 0x01 53#define ACP_SHA_RUN 0x01 54#define ACP_SHA_RESET 0x02 55#define ACP_SHA_HEADER 0x01 --- 5 unchanged lines hidden (view full) --- 61 62#define ACP_DEFAULT_DRAM_LENGTH 0x00080000 63#define ACP3X_SCRATCH_MEMORY_ADDRESS 0x02050000 64#define ACP_SYSTEM_MEMORY_WINDOW 0x4000000 65#define ACP_IRAM_BASE_ADDRESS 0x000000 66#define ACP_DRAM_BASE_ADDRESS 0x01000000 67#define ACP_DRAM_PAGE_COUNT 128 68#define ACP_SRAM_BASE_ADDRESS 0x3806000 |
| 69#define ACP7X_SRAM_BASE_ADDRESS 0x380C000 |
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| 66#define ACP_DSP_TO_HOST_IRQ 0x04 67 68#define ACP_RN_PCI_ID 0x01 69#define ACP_VANGOGH_PCI_ID 0x50 70#define ACP_RMB_PCI_ID 0x6F 71#define ACP63_PCI_ID 0x63 | 70#define ACP_DSP_TO_HOST_IRQ 0x04 71 72#define ACP_RN_PCI_ID 0x01 73#define ACP_VANGOGH_PCI_ID 0x50 74#define ACP_RMB_PCI_ID 0x6F 75#define ACP63_PCI_ID 0x63 |
| 76#define ACP70_PCI_ID 0x70 |
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| 72 73#define HOST_BRIDGE_CZN 0x1630 74#define HOST_BRIDGE_VGH 0x1645 75#define HOST_BRIDGE_RMB 0x14B5 76#define HOST_BRIDGE_ACP63 0x14E8 | 77 78#define HOST_BRIDGE_CZN 0x1630 79#define HOST_BRIDGE_VGH 0x1645 80#define HOST_BRIDGE_RMB 0x14B5 81#define HOST_BRIDGE_ACP63 0x14E8 |
| 82#define HOST_BRIDGE_ACP70 0x1507 |
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| 77#define ACP_SHA_STAT 0x8000 78#define ACP_PSP_TIMEOUT_US 1000000 79#define ACP_EXT_INTR_ERROR_STAT 0x20000000 80#define MP0_C2PMSG_114_REG 0x3810AC8 81#define MP0_C2PMSG_73_REG 0x3810A24 82#define MBOX_ACP_SHA_DMA_COMMAND 0x70000 83#define MBOX_ACP_IRAM_DRAM_FENCE_COMMAND 0x80000 84#define MBOX_DELAY_US 1000 --- 236 unchanged lines hidden (view full) --- 321int sof_renoir_ops_init(struct snd_sof_dev *sdev); 322extern struct snd_sof_dsp_ops sof_vangogh_ops; 323int sof_vangogh_ops_init(struct snd_sof_dev *sdev); 324extern struct snd_sof_dsp_ops sof_rembrandt_ops; 325int sof_rembrandt_ops_init(struct snd_sof_dev *sdev); 326extern struct snd_sof_dsp_ops sof_acp63_ops; 327int sof_acp63_ops_init(struct snd_sof_dev *sdev); 328 | 83#define ACP_SHA_STAT 0x8000 84#define ACP_PSP_TIMEOUT_US 1000000 85#define ACP_EXT_INTR_ERROR_STAT 0x20000000 86#define MP0_C2PMSG_114_REG 0x3810AC8 87#define MP0_C2PMSG_73_REG 0x3810A24 88#define MBOX_ACP_SHA_DMA_COMMAND 0x70000 89#define MBOX_ACP_IRAM_DRAM_FENCE_COMMAND 0x80000 90#define MBOX_DELAY_US 1000 --- 236 unchanged lines hidden (view full) --- 327int sof_renoir_ops_init(struct snd_sof_dev *sdev); 328extern struct snd_sof_dsp_ops sof_vangogh_ops; 329int sof_vangogh_ops_init(struct snd_sof_dev *sdev); 330extern struct snd_sof_dsp_ops sof_rembrandt_ops; 331int sof_rembrandt_ops_init(struct snd_sof_dev *sdev); 332extern struct snd_sof_dsp_ops sof_acp63_ops; 333int sof_acp63_ops_init(struct snd_sof_dev *sdev); 334 |
| 335extern struct snd_sof_dsp_ops sof_acp70_ops; 336int sof_acp70_ops_init(struct snd_sof_dev *sdev); 337 |
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| 329struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev); 330/* Machine configuration */ 331int snd_amd_acp_find_config(struct pci_dev *pci); 332 333/* Trace */ 334int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 335 struct sof_ipc_dma_trace_params_ext *dtrace_params); 336int acp_sof_trace_release(struct snd_sof_dev *sdev); --- 21 unchanged lines hidden --- | 338struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev); 339/* Machine configuration */ 340int snd_amd_acp_find_config(struct pci_dev *pci); 341 342/* Trace */ 343int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 344 struct sof_ipc_dma_trace_params_ext *dtrace_params); 345int acp_sof_trace_release(struct snd_sof_dev *sdev); --- 21 unchanged lines hidden --- |