1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7 * 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 9 */ 10 11 #ifndef __SOF_AMD_ACP_H 12 #define __SOF_AMD_ACP_H 13 14 #include <linux/dmi.h> 15 #include <linux/soundwire/sdw_amd.h> 16 #include "../sof-priv.h" 17 #include "../sof-audio.h" 18 19 #define ACP_MAX_STREAM 8 20 21 #define ACP_DSP_BAR 0 22 23 #define ACP_HW_SEM_RETRY_COUNT 10000 24 #define ACP_REG_POLL_INTERVAL 500 25 #define ACP_REG_POLL_TIMEOUT_US 2000 26 #define ACP_DMA_COMPLETE_TIMEOUT_US 5000 27 28 #define ACP3X_PGFSM_CNTL_POWER_ON_MASK 0x01 29 #define ACP3X_PGFSM_STATUS_MASK 0x03 30 #define ACP6X_PGFSM_CNTL_POWER_ON_MASK 0x07 31 #define ACP6X_PGFSM_STATUS_MASK 0x0F 32 33 #define ACP_POWERED_ON 0x00 34 #define ACP_ASSERT_RESET 0x01 35 #define ACP_RELEASE_RESET 0x00 36 #define ACP_SOFT_RESET_DONE_MASK 0x00010001 37 #define ACP_DSP_ASSERT_RESET 0x04 38 #define ACP_DSP_RELEASE_RESET 0x00 39 #define ACP_DSP_SOFT_RESET_DONE_MASK 0x00050004 40 41 #define ACP_DSP_INTR_EN_MASK 0x00000001 42 #define ACP3X_SRAM_PTE_OFFSET 0x02050000 43 #define ACP5X_SRAM_PTE_OFFSET 0x02050000 44 #define ACP6X_SRAM_PTE_OFFSET 0x03800000 45 #define PAGE_SIZE_4K_ENABLE 0x2 46 #define ACP_PAGE_SIZE 0x1000 47 #define ACP_DMA_CH_RUN 0x02 48 #define ACP_MAX_DESC_CNT 0x02 49 #define DSP_FW_RUN_ENABLE 0x01 50 #define ACP_SHA_RUN 0x01 51 #define ACP_SHA_RESET 0x02 52 #define ACP_SHA_HEADER 0x01 53 #define ACP_DMA_CH_RST 0x01 54 #define ACP_DMA_CH_GRACEFUL_RST_EN 0x10 55 #define ACP_ATU_CACHE_INVALID 0x01 56 #define ACP_MAX_DESC 128 57 #define ACPBUS_REG_BASE_OFFSET ACP_DMA_CNTL_0 58 59 #define ACP_DEFAULT_DRAM_LENGTH 0x00080000 60 #define ACP3X_SCRATCH_MEMORY_ADDRESS 0x02050000 61 #define ACP_SYSTEM_MEMORY_WINDOW 0x4000000 62 #define ACP_IRAM_BASE_ADDRESS 0x000000 63 #define ACP_DRAM_BASE_ADDRESS 0x01000000 64 #define ACP_DRAM_PAGE_COUNT 128 65 #define ACP_SRAM_BASE_ADDRESS 0x3806000 66 #define ACP_DSP_TO_HOST_IRQ 0x04 67 68 #define ACP_RN_PCI_ID 0x01 69 #define ACP_VANGOGH_PCI_ID 0x50 70 #define ACP_RMB_PCI_ID 0x6F 71 #define ACP63_PCI_ID 0x63 72 73 #define HOST_BRIDGE_CZN 0x1630 74 #define HOST_BRIDGE_VGH 0x1645 75 #define HOST_BRIDGE_RMB 0x14B5 76 #define HOST_BRIDGE_ACP63 0x14E8 77 #define ACP_SHA_STAT 0x8000 78 #define ACP_PSP_TIMEOUT_US 1000000 79 #define ACP_EXT_INTR_ERROR_STAT 0x20000000 80 #define MP0_C2PMSG_114_REG 0x3810AC8 81 #define MP0_C2PMSG_73_REG 0x3810A24 82 #define MBOX_ACP_SHA_DMA_COMMAND 0x70000 83 #define MBOX_ACP_IRAM_DRAM_FENCE_COMMAND 0x80000 84 #define MBOX_DELAY_US 1000 85 #define MBOX_READY_MASK 0x80000000 86 #define MBOX_STATUS_MASK 0xFFFF 87 #define MBOX_ISREADY_FLAG 0x40000000 88 #define IRAM_DRAM_FENCE_0 0X0 89 #define IRAM_DRAM_FENCE_1 0X01 90 #define IRAM_DRAM_FENCE_2 0X02 91 92 #define BOX_SIZE_512 0x200 93 #define BOX_SIZE_1024 0x400 94 95 #define EXCEPT_MAX_HDR_SIZE 0x400 96 #define AMD_STACK_DUMP_SIZE 32 97 98 #define SRAM1_SIZE 0x280000 99 #define PROBE_STATUS_BIT BIT(31) 100 101 #define ACP_FIRMWARE_SIGNATURE 0x100 102 #define ACP_ERROR_IRQ_MASK BIT(29) 103 #define ACP_SDW0_IRQ_MASK BIT(21) 104 #define ACP_SDW1_IRQ_MASK BIT(2) 105 #define SDW_ACPI_ADDR_ACP63 5 106 #define ACP_DEFAULT_SRAM_LENGTH 0x00080000 107 #define ACP_SRAM_PAGE_COUNT 128 108 #define ACP6X_SDW_MAX_MANAGER_COUNT 2 109 110 enum clock_source { 111 ACP_CLOCK_96M = 0, 112 ACP_CLOCK_48M, 113 ACP_CLOCK_24M, 114 ACP_CLOCK_ACLK, 115 ACP_CLOCK_MCLK, 116 }; 117 118 struct acp_atu_grp_pte { 119 u32 low; 120 u32 high; 121 }; 122 123 union dma_tx_cnt { 124 struct { 125 unsigned int count : 19; 126 unsigned int reserved : 12; 127 unsigned ioc : 1; 128 } bitfields, bits; 129 unsigned int u32_all; 130 signed int i32_all; 131 }; 132 133 struct dma_descriptor { 134 unsigned int src_addr; 135 unsigned int dest_addr; 136 union dma_tx_cnt tx_cnt; 137 unsigned int reserved; 138 }; 139 140 /* Scratch memory structure for communication b/w host and dsp */ 141 struct scratch_ipc_conf { 142 /* Debug memory */ 143 u8 sof_debug_box[1024]; 144 /* Exception memory*/ 145 u8 sof_except_box[1024]; 146 /* Stream buffer */ 147 u8 sof_stream_box[1024]; 148 /* Trace buffer */ 149 u8 sof_trace_box[1024]; 150 /* Host msg flag */ 151 u32 sof_host_msg_write; 152 /* Host ack flag*/ 153 u32 sof_host_ack_write; 154 /* DSP msg flag */ 155 u32 sof_dsp_msg_write; 156 /* Dsp ack flag */ 157 u32 sof_dsp_ack_write; 158 }; 159 160 struct scratch_reg_conf { 161 struct scratch_ipc_conf info; 162 struct acp_atu_grp_pte grp1_pte[16]; 163 struct acp_atu_grp_pte grp2_pte[16]; 164 struct acp_atu_grp_pte grp3_pte[16]; 165 struct acp_atu_grp_pte grp4_pte[16]; 166 struct acp_atu_grp_pte grp5_pte[16]; 167 struct acp_atu_grp_pte grp6_pte[16]; 168 struct acp_atu_grp_pte grp7_pte[16]; 169 struct acp_atu_grp_pte grp8_pte[16]; 170 struct dma_descriptor dma_desc[64]; 171 unsigned int reg_offset[8]; 172 unsigned int buf_size[8]; 173 u8 acp_tx_fifo_buf[256]; 174 u8 acp_rx_fifo_buf[256]; 175 unsigned int reserve[]; 176 }; 177 178 struct acp_dsp_stream { 179 struct list_head list; 180 struct snd_sof_dev *sdev; 181 struct snd_pcm_substream *substream; 182 struct snd_dma_buffer *dmab; 183 int num_pages; 184 int stream_tag; 185 int active; 186 unsigned int reg_offset; 187 size_t posn_offset; 188 struct snd_compr_stream *cstream; 189 u64 cstream_posn; 190 }; 191 192 struct sof_amd_acp_desc { 193 const char *name; 194 unsigned int host_bridge_id; 195 u32 pgfsm_base; 196 u32 ext_intr_enb; 197 u32 ext_intr_cntl; 198 u32 ext_intr_stat; 199 u32 ext_intr_stat1; 200 u32 dsp_intr_base; 201 u32 sram_pte_offset; 202 u32 hw_semaphore_offset; 203 u32 acp_clkmux_sel; 204 u32 fusion_dsp_offset; 205 u32 probe_reg_offset; 206 u32 reg_start_addr; 207 u32 reg_end_addr; 208 u32 acp_error_stat; 209 u32 acp_sw0_i2s_err_reason; 210 u32 sdw_max_link_count; 211 u64 sdw_acpi_dev_addr; 212 }; 213 214 struct acp_quirk_entry { 215 bool signed_fw_image; 216 bool skip_iram_dram_size_mod; 217 }; 218 219 /* Common device data struct for ACP devices */ 220 struct acp_dev_data { 221 struct snd_sof_dev *dev; 222 const struct firmware *fw_dbin; 223 /* DMIC device */ 224 struct platform_device *dmic_dev; 225 /* mutex lock to protect ACP common registers access */ 226 struct mutex acp_lock; 227 /* ACPI information stored between scan and probe steps */ 228 struct sdw_amd_acpi_info info; 229 /* sdw context allocated by SoundWire driver */ 230 struct sdw_amd_ctx *sdw; 231 unsigned int fw_bin_size; 232 unsigned int fw_data_bin_size; 233 unsigned int fw_sram_data_bin_size; 234 const char *fw_code_bin; 235 const char *fw_data_bin; 236 const char *fw_sram_data_bin; 237 u32 fw_bin_page_count; 238 u32 fw_data_bin_page_count; 239 u32 addr; 240 u32 reg_range; 241 u32 blk_type; 242 dma_addr_t sha_dma_addr; 243 u8 *bin_buf; 244 dma_addr_t dma_addr; 245 u8 *data_buf; 246 dma_addr_t sram_dma_addr; 247 u8 *sram_data_buf; 248 struct acp_quirk_entry *quirks; 249 struct dma_descriptor dscr_info[ACP_MAX_DESC]; 250 struct acp_dsp_stream stream_buf[ACP_MAX_STREAM]; 251 struct acp_dsp_stream *dtrace_stream; 252 struct pci_dev *smn_dev; 253 struct acp_dsp_stream *probe_stream; 254 bool enable_fw_debug; 255 bool is_dram_in_use; 256 bool is_sram_in_use; 257 bool sdw_en_stat; 258 unsigned int pci_rev; 259 }; 260 261 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes); 262 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes); 263 264 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch); 265 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 266 unsigned int dest_addr, int dsp_data_size); 267 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 268 unsigned int start_addr, unsigned int dest_addr, 269 unsigned int image_length); 270 271 /* ACP device probe/remove */ 272 int amd_sof_acp_probe(struct snd_sof_dev *sdev); 273 void amd_sof_acp_remove(struct snd_sof_dev *sdev); 274 275 /* DSP Loader callbacks */ 276 int acp_sof_dsp_run(struct snd_sof_dev *sdev); 277 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev); 278 int acp_sof_load_signed_firmware(struct snd_sof_dev *sdev); 279 int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type); 280 281 /* Block IO callbacks */ 282 int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 283 u32 offset, void *src, size_t size); 284 int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 285 u32 offset, void *dest, size_t size); 286 287 /* IPC callbacks */ 288 irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context); 289 int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps, 290 void *p, size_t sz); 291 int acp_set_stream_data_offset(struct snd_sof_dev *sdev, 292 struct snd_sof_pcm_stream *sps, 293 size_t posn_offset); 294 int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, 295 struct snd_sof_ipc_msg *msg); 296 int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 297 int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 298 void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 299 void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 300 301 /* ACP - DSP stream callbacks */ 302 int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *stream); 303 int acp_dsp_stream_init(struct snd_sof_dev *sdev); 304 struct acp_dsp_stream *acp_dsp_stream_get(struct snd_sof_dev *sdev, int tag); 305 int acp_dsp_stream_put(struct snd_sof_dev *sdev, struct acp_dsp_stream *acp_stream); 306 307 /* 308 * DSP PCM Operations. 309 */ 310 int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 311 int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 312 int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream, 313 struct snd_pcm_hw_params *params, 314 struct snd_sof_platform_stream_params *platform_params); 315 snd_pcm_uframes_t acp_pcm_pointer(struct snd_sof_dev *sdev, 316 struct snd_pcm_substream *substream); 317 318 extern const struct snd_sof_dsp_ops sof_acp_common_ops; 319 320 extern struct snd_sof_dsp_ops sof_renoir_ops; 321 int sof_renoir_ops_init(struct snd_sof_dev *sdev); 322 extern struct snd_sof_dsp_ops sof_vangogh_ops; 323 int sof_vangogh_ops_init(struct snd_sof_dev *sdev); 324 extern struct snd_sof_dsp_ops sof_rembrandt_ops; 325 int sof_rembrandt_ops_init(struct snd_sof_dev *sdev); 326 extern struct snd_sof_dsp_ops sof_acp63_ops; 327 int sof_acp63_ops_init(struct snd_sof_dev *sdev); 328 329 struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev); 330 /* Machine configuration */ 331 int snd_amd_acp_find_config(struct pci_dev *pci); 332 333 /* Trace */ 334 int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 335 struct sof_ipc_dma_trace_params_ext *dtrace_params); 336 int acp_sof_trace_release(struct snd_sof_dev *sdev); 337 338 /* PM Callbacks */ 339 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state); 340 int amd_sof_acp_resume(struct snd_sof_dev *sdev); 341 342 void amd_sof_ipc_dump(struct snd_sof_dev *sdev); 343 void amd_sof_dump(struct snd_sof_dev *sdev, u32 flags); 344 345 static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata) 346 { 347 const struct sof_dev_desc *desc = pdata->desc; 348 349 return desc->chip_info; 350 } 351 352 int acp_probes_register(struct snd_sof_dev *sdev); 353 void acp_probes_unregister(struct snd_sof_dev *sdev); 354 355 extern struct snd_soc_acpi_mach snd_soc_acpi_amd_vangogh_sof_machines[]; 356 extern const struct dmi_system_id acp_sof_quirk_table[]; 357 #endif 358