acp.h (41c177cf354126a22443b5c80cec9fdd313e67e1) acp.h (d948218424bf9194860fcc10259ff42487cf4bd9)
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
7 *
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
9 */
10
11#ifndef __SOF_AMD_ACP_H
12#define __SOF_AMD_ACP_H
13
14#include <linux/dmi.h>
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
7 *
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
9 */
10
11#ifndef __SOF_AMD_ACP_H
12#define __SOF_AMD_ACP_H
13
14#include <linux/dmi.h>
15
15#include <linux/soundwire/sdw_amd.h>
16#include "../sof-priv.h"
17#include "../sof-audio.h"
18
19#define ACP_MAX_STREAM 8
20
21#define ACP_DSP_BAR 0
22
23#define ACP_HW_SEM_RETRY_COUNT 10000

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186 u32 ext_intr_enb;
187 u32 ext_intr_stat;
188 u32 dsp_intr_base;
189 u32 sram_pte_offset;
190 u32 hw_semaphore_offset;
191 u32 acp_clkmux_sel;
192 u32 fusion_dsp_offset;
193 u32 probe_reg_offset;
16#include "../sof-priv.h"
17#include "../sof-audio.h"
18
19#define ACP_MAX_STREAM 8
20
21#define ACP_DSP_BAR 0
22
23#define ACP_HW_SEM_RETRY_COUNT 10000

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186 u32 ext_intr_enb;
187 u32 ext_intr_stat;
188 u32 dsp_intr_base;
189 u32 sram_pte_offset;
190 u32 hw_semaphore_offset;
191 u32 acp_clkmux_sel;
192 u32 fusion_dsp_offset;
193 u32 probe_reg_offset;
194 u32 reg_start_addr;
195 u32 reg_end_addr;
196 u32 sdw_max_link_count;
197 u64 sdw_acpi_dev_addr;
194};
195
196/* Common device data struct for ACP devices */
197struct acp_dev_data {
198 struct snd_sof_dev *dev;
199 const struct firmware *fw_dbin;
200 /* DMIC device */
201 struct platform_device *dmic_dev;
198};
199
200/* Common device data struct for ACP devices */
201struct acp_dev_data {
202 struct snd_sof_dev *dev;
203 const struct firmware *fw_dbin;
204 /* DMIC device */
205 struct platform_device *dmic_dev;
206 /* mutex lock to protect ACP common registers access */
207 struct mutex acp_lock;
208 /* ACPI information stored between scan and probe steps */
209 struct sdw_amd_acpi_info info;
210 /* sdw context allocated by SoundWire driver */
211 struct sdw_amd_ctx *sdw;
202 unsigned int fw_bin_size;
203 unsigned int fw_data_bin_size;
204 unsigned int fw_sram_data_bin_size;
205 const char *fw_code_bin;
206 const char *fw_data_bin;
207 const char *fw_sram_data_bin;
208 u32 fw_bin_page_count;
209 u32 fw_data_bin_page_count;
212 unsigned int fw_bin_size;
213 unsigned int fw_data_bin_size;
214 unsigned int fw_sram_data_bin_size;
215 const char *fw_code_bin;
216 const char *fw_data_bin;
217 const char *fw_sram_data_bin;
218 u32 fw_bin_page_count;
219 u32 fw_data_bin_page_count;
220 u32 addr;
221 u32 reg_range;
222 u32 blk_type;
210 dma_addr_t sha_dma_addr;
211 u8 *bin_buf;
212 dma_addr_t dma_addr;
213 u8 *data_buf;
214 dma_addr_t sram_dma_addr;
215 u8 *sram_data_buf;
216 bool signed_fw_image;
217 struct dma_descriptor dscr_info[ACP_MAX_DESC];

--- 106 unchanged lines hidden --- 		223 dma_addr_t sha_dma_addr;
224 u8 *bin_buf;
225 dma_addr_t dma_addr;
226 u8 *data_buf;
227 dma_addr_t sram_dma_addr;
228 u8 *sram_data_buf;
229 bool signed_fw_image;
230 struct dma_descriptor dscr_info[ACP_MAX_DESC];

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