1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7 * 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 9 */ 10 11 #ifndef __SOF_AMD_ACP_H 12 #define __SOF_AMD_ACP_H 13 14 #include <linux/dmi.h> 15 #include <linux/soundwire/sdw_amd.h> 16 #include "../sof-priv.h" 17 #include "../sof-audio.h" 18 19 #define ACP_MAX_STREAM 8 20 21 #define ACP_DSP_BAR 0 22 23 #define ACP_HW_SEM_RETRY_COUNT 10000 24 #define ACP_REG_POLL_INTERVAL 500 25 #define ACP_REG_POLL_TIMEOUT_US 2000 26 #define ACP_DMA_COMPLETE_TIMEOUT_US 5000 27 28 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01 29 #define ACP_PGFSM_STATUS_MASK 0x03 30 #define ACP_POWERED_ON 0x00 31 #define ACP_ASSERT_RESET 0x01 32 #define ACP_RELEASE_RESET 0x00 33 #define ACP_SOFT_RESET_DONE_MASK 0x00010001 34 35 #define ACP_DSP_INTR_EN_MASK 0x00000001 36 #define ACP3X_SRAM_PTE_OFFSET 0x02050000 37 #define ACP5X_SRAM_PTE_OFFSET 0x02050000 38 #define ACP6X_SRAM_PTE_OFFSET 0x03800000 39 #define PAGE_SIZE_4K_ENABLE 0x2 40 #define ACP_PAGE_SIZE 0x1000 41 #define ACP_DMA_CH_RUN 0x02 42 #define ACP_MAX_DESC_CNT 0x02 43 #define DSP_FW_RUN_ENABLE 0x01 44 #define ACP_SHA_RUN 0x01 45 #define ACP_SHA_RESET 0x02 46 #define ACP_SHA_HEADER 0x01 47 #define ACP_DMA_CH_RST 0x01 48 #define ACP_DMA_CH_GRACEFUL_RST_EN 0x10 49 #define ACP_ATU_CACHE_INVALID 0x01 50 #define ACP_MAX_DESC 128 51 #define ACPBUS_REG_BASE_OFFSET ACP_DMA_CNTL_0 52 53 #define ACP_DEFAULT_DRAM_LENGTH 0x00080000 54 #define ACP3X_SCRATCH_MEMORY_ADDRESS 0x02050000 55 #define ACP_SYSTEM_MEMORY_WINDOW 0x4000000 56 #define ACP_IRAM_BASE_ADDRESS 0x000000 57 #define ACP_DRAM_BASE_ADDRESS 0x01000000 58 #define ACP_DRAM_PAGE_COUNT 128 59 #define ACP_SRAM_BASE_ADDRESS 0x3806000 60 #define ACP_DSP_TO_HOST_IRQ 0x04 61 62 #define ACP_RN_PCI_ID 0x01 63 #define ACP_VANGOGH_PCI_ID 0x50 64 #define ACP_RMB_PCI_ID 0x6F 65 #define ACP63_PCI_ID 0x63 66 67 #define HOST_BRIDGE_CZN 0x1630 68 #define HOST_BRIDGE_VGH 0x1645 69 #define HOST_BRIDGE_RMB 0x14B5 70 #define HOST_BRIDGE_ACP63 0x14E8 71 #define ACP_SHA_STAT 0x8000 72 #define ACP_PSP_TIMEOUT_US 1000000 73 #define ACP_EXT_INTR_ERROR_STAT 0x20000000 74 #define MP0_C2PMSG_114_REG 0x3810AC8 75 #define MP0_C2PMSG_73_REG 0x3810A24 76 #define MBOX_ACP_SHA_DMA_COMMAND 0x70000 77 #define MBOX_ACP_IRAM_DRAM_FENCE_COMMAND 0x80000 78 #define MBOX_DELAY_US 1000 79 #define MBOX_READY_MASK 0x80000000 80 #define MBOX_STATUS_MASK 0xFFFF 81 #define MBOX_ISREADY_FLAG 0x40000000 82 #define IRAM_DRAM_FENCE_0 0X0 83 #define IRAM_DRAM_FENCE_1 0X01 84 #define IRAM_DRAM_FENCE_2 0X02 85 86 #define BOX_SIZE_512 0x200 87 #define BOX_SIZE_1024 0x400 88 89 #define EXCEPT_MAX_HDR_SIZE 0x400 90 #define AMD_STACK_DUMP_SIZE 32 91 92 #define SRAM1_SIZE 0x280000 93 #define PROBE_STATUS_BIT BIT(31) 94 95 #define ACP_FIRMWARE_SIGNATURE 0x100 96 #define ACP_DEFAULT_SRAM_LENGTH 0x00080000 97 #define ACP_SRAM_PAGE_COUNT 128 98 99 enum clock_source { 100 ACP_CLOCK_96M = 0, 101 ACP_CLOCK_48M, 102 ACP_CLOCK_24M, 103 ACP_CLOCK_ACLK, 104 ACP_CLOCK_MCLK, 105 }; 106 107 struct acp_atu_grp_pte { 108 u32 low; 109 u32 high; 110 }; 111 112 union dma_tx_cnt { 113 struct { 114 unsigned int count : 19; 115 unsigned int reserved : 12; 116 unsigned ioc : 1; 117 } bitfields, bits; 118 unsigned int u32_all; 119 signed int i32_all; 120 }; 121 122 struct dma_descriptor { 123 unsigned int src_addr; 124 unsigned int dest_addr; 125 union dma_tx_cnt tx_cnt; 126 unsigned int reserved; 127 }; 128 129 /* Scratch memory structure for communication b/w host and dsp */ 130 struct scratch_ipc_conf { 131 /* Debug memory */ 132 u8 sof_debug_box[1024]; 133 /* Exception memory*/ 134 u8 sof_except_box[1024]; 135 /* Stream buffer */ 136 u8 sof_stream_box[1024]; 137 /* Trace buffer */ 138 u8 sof_trace_box[1024]; 139 /* Host msg flag */ 140 u32 sof_host_msg_write; 141 /* Host ack flag*/ 142 u32 sof_host_ack_write; 143 /* DSP msg flag */ 144 u32 sof_dsp_msg_write; 145 /* Dsp ack flag */ 146 u32 sof_dsp_ack_write; 147 }; 148 149 struct scratch_reg_conf { 150 struct scratch_ipc_conf info; 151 struct acp_atu_grp_pte grp1_pte[16]; 152 struct acp_atu_grp_pte grp2_pte[16]; 153 struct acp_atu_grp_pte grp3_pte[16]; 154 struct acp_atu_grp_pte grp4_pte[16]; 155 struct acp_atu_grp_pte grp5_pte[16]; 156 struct acp_atu_grp_pte grp6_pte[16]; 157 struct acp_atu_grp_pte grp7_pte[16]; 158 struct acp_atu_grp_pte grp8_pte[16]; 159 struct dma_descriptor dma_desc[64]; 160 unsigned int reg_offset[8]; 161 unsigned int buf_size[8]; 162 u8 acp_tx_fifo_buf[256]; 163 u8 acp_rx_fifo_buf[256]; 164 unsigned int reserve[]; 165 }; 166 167 struct acp_dsp_stream { 168 struct list_head list; 169 struct snd_sof_dev *sdev; 170 struct snd_pcm_substream *substream; 171 struct snd_dma_buffer *dmab; 172 int num_pages; 173 int stream_tag; 174 int active; 175 unsigned int reg_offset; 176 size_t posn_offset; 177 struct snd_compr_stream *cstream; 178 u64 cstream_posn; 179 }; 180 181 struct sof_amd_acp_desc { 182 unsigned int rev; 183 const char *name; 184 unsigned int host_bridge_id; 185 u32 pgfsm_base; 186 u32 ext_intr_enb; 187 u32 ext_intr_stat; 188 u32 dsp_intr_base; 189 u32 sram_pte_offset; 190 u32 hw_semaphore_offset; 191 u32 acp_clkmux_sel; 192 u32 fusion_dsp_offset; 193 u32 probe_reg_offset; 194 u32 reg_start_addr; 195 u32 reg_end_addr; 196 u32 sdw_max_link_count; 197 u64 sdw_acpi_dev_addr; 198 }; 199 200 /* Common device data struct for ACP devices */ 201 struct acp_dev_data { 202 struct snd_sof_dev *dev; 203 const struct firmware *fw_dbin; 204 /* DMIC device */ 205 struct platform_device *dmic_dev; 206 /* mutex lock to protect ACP common registers access */ 207 struct mutex acp_lock; 208 /* ACPI information stored between scan and probe steps */ 209 struct sdw_amd_acpi_info info; 210 /* sdw context allocated by SoundWire driver */ 211 struct sdw_amd_ctx *sdw; 212 unsigned int fw_bin_size; 213 unsigned int fw_data_bin_size; 214 unsigned int fw_sram_data_bin_size; 215 const char *fw_code_bin; 216 const char *fw_data_bin; 217 const char *fw_sram_data_bin; 218 u32 fw_bin_page_count; 219 u32 fw_data_bin_page_count; 220 u32 addr; 221 u32 reg_range; 222 u32 blk_type; 223 dma_addr_t sha_dma_addr; 224 u8 *bin_buf; 225 dma_addr_t dma_addr; 226 u8 *data_buf; 227 dma_addr_t sram_dma_addr; 228 u8 *sram_data_buf; 229 bool signed_fw_image; 230 struct dma_descriptor dscr_info[ACP_MAX_DESC]; 231 struct acp_dsp_stream stream_buf[ACP_MAX_STREAM]; 232 struct acp_dsp_stream *dtrace_stream; 233 struct pci_dev *smn_dev; 234 struct acp_dsp_stream *probe_stream; 235 bool enable_fw_debug; 236 bool is_dram_in_use; 237 bool is_sram_in_use; 238 }; 239 240 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes); 241 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes); 242 243 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch); 244 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 245 unsigned int dest_addr, int dsp_data_size); 246 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 247 unsigned int start_addr, unsigned int dest_addr, 248 unsigned int image_length); 249 250 /* ACP device probe/remove */ 251 int amd_sof_acp_probe(struct snd_sof_dev *sdev); 252 void amd_sof_acp_remove(struct snd_sof_dev *sdev); 253 254 /* DSP Loader callbacks */ 255 int acp_sof_dsp_run(struct snd_sof_dev *sdev); 256 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev); 257 int acp_sof_load_signed_firmware(struct snd_sof_dev *sdev); 258 int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type); 259 260 /* Block IO callbacks */ 261 int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 262 u32 offset, void *src, size_t size); 263 int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 264 u32 offset, void *dest, size_t size); 265 266 /* IPC callbacks */ 267 irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context); 268 int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps, 269 void *p, size_t sz); 270 int acp_set_stream_data_offset(struct snd_sof_dev *sdev, 271 struct snd_sof_pcm_stream *sps, 272 size_t posn_offset); 273 int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, 274 struct snd_sof_ipc_msg *msg); 275 int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 276 int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 277 void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 278 void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 279 280 /* ACP - DSP stream callbacks */ 281 int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *stream); 282 int acp_dsp_stream_init(struct snd_sof_dev *sdev); 283 struct acp_dsp_stream *acp_dsp_stream_get(struct snd_sof_dev *sdev, int tag); 284 int acp_dsp_stream_put(struct snd_sof_dev *sdev, struct acp_dsp_stream *acp_stream); 285 286 /* 287 * DSP PCM Operations. 288 */ 289 int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 290 int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 291 int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream, 292 struct snd_pcm_hw_params *params, 293 struct snd_sof_platform_stream_params *platform_params); 294 snd_pcm_uframes_t acp_pcm_pointer(struct snd_sof_dev *sdev, 295 struct snd_pcm_substream *substream); 296 297 extern struct snd_sof_dsp_ops sof_acp_common_ops; 298 299 extern struct snd_sof_dsp_ops sof_renoir_ops; 300 int sof_renoir_ops_init(struct snd_sof_dev *sdev); 301 extern struct snd_sof_dsp_ops sof_vangogh_ops; 302 int sof_vangogh_ops_init(struct snd_sof_dev *sdev); 303 extern struct snd_sof_dsp_ops sof_rembrandt_ops; 304 int sof_rembrandt_ops_init(struct snd_sof_dev *sdev); 305 extern struct snd_sof_dsp_ops sof_acp63_ops; 306 int sof_acp63_ops_init(struct snd_sof_dev *sdev); 307 308 struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev); 309 /* Machine configuration */ 310 int snd_amd_acp_find_config(struct pci_dev *pci); 311 312 /* Trace */ 313 int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 314 struct sof_ipc_dma_trace_params_ext *dtrace_params); 315 int acp_sof_trace_release(struct snd_sof_dev *sdev); 316 317 /* PM Callbacks */ 318 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state); 319 int amd_sof_acp_resume(struct snd_sof_dev *sdev); 320 321 void amd_sof_ipc_dump(struct snd_sof_dev *sdev); 322 void amd_sof_dump(struct snd_sof_dev *sdev, u32 flags); 323 324 static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata) 325 { 326 const struct sof_dev_desc *desc = pdata->desc; 327 328 return desc->chip_info; 329 } 330 331 int acp_probes_register(struct snd_sof_dev *sdev); 332 void acp_probes_unregister(struct snd_sof_dev *sdev); 333 334 extern struct snd_soc_acpi_mach snd_soc_acpi_amd_vangogh_sof_machines[]; 335 extern const struct dmi_system_id acp_sof_quirk_table[]; 336 #endif 337