tlv320aic32x4.c (514b044cba667e4b7c383ec79b42b997e624b91d) tlv320aic32x4.c (fd2df3aeafa4b4cc468d58e147e0822967034b71)
1/*
2 * linux/sound/soc/codecs/tlv320aic32x4.c
3 *
4 * Copyright 2011 Vista Silicon S.L.
5 *
6 * Author: Javier Martin <javier.martin@vista-silicon.com>
7 *
8 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.

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730 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
731 if (ret)
732 return ret;
733
734 clk_set_rate(clocks[0].clk, sample_rate);
735
736 aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block);
737
1/*
2 * linux/sound/soc/codecs/tlv320aic32x4.c
3 *
4 * Copyright 2011 Vista Silicon S.L.
5 *
6 * Author: Javier Martin <javier.martin@vista-silicon.com>
7 *
8 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.

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730 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
731 if (ret)
732 return ret;
733
734 clk_set_rate(clocks[0].clk, sample_rate);
735
736 aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block);
737
738 /* PLL as CODEC_CLKIN */
739 snd_soc_component_update_bits(component, AIC32X4_CLKMUX,
740 AIC32X4_CODEC_CLKIN_MASK,
741 AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT);
742 /* DAC_MOD_CLK as BDIV_CLKIN */
738 /* DAC_MOD_CLK as BDIV_CLKIN */
743 snd_soc_component_update_bits(component, AIC32X4_IFACE3, AIC32X4_BDIVCLK_MASK,
739 snd_soc_component_update_bits(component, AIC32X4_IFACE3,
740 AIC32X4_BDIVCLK_MASK,
744 AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT);
745
746 /* NDAC divider value */
747 snd_soc_component_update_bits(component, AIC32X4_NDAC,
748 AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac);
749
750 /* MDAC divider value */
751 snd_soc_component_update_bits(component, AIC32X4_MDAC,

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982 ARRAY_SIZE(aic32x4_mfp5));
983 }
984}
985
986static int aic32x4_component_probe(struct snd_soc_component *component)
987{
988 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
989 u32 tmp_reg;
741 AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT);
742
743 /* NDAC divider value */
744 snd_soc_component_update_bits(component, AIC32X4_NDAC,
745 AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac);
746
747 /* MDAC divider value */
748 snd_soc_component_update_bits(component, AIC32X4_MDAC,

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979 ARRAY_SIZE(aic32x4_mfp5));
980 }
981}
982
983static int aic32x4_component_probe(struct snd_soc_component *component)
984{
985 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
986 u32 tmp_reg;
987 int ret;
990
988
989 struct clk_bulk_data clocks[] = {
990 { .id = "codec_clkin" },
991 };
992
993 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
994 if (ret)
995 return ret;
996
991 if (gpio_is_valid(aic32x4->rstn_gpio)) {
992 ndelay(10);
993 gpio_set_value(aic32x4->rstn_gpio, 1);
994 mdelay(1);
995 }
996
997 snd_soc_component_write(component, AIC32X4_RESET, 0x01);
998
999 if (aic32x4->setup)
1000 aic32x4_setup_gpios(component);
1001
997 if (gpio_is_valid(aic32x4->rstn_gpio)) {
998 ndelay(10);
999 gpio_set_value(aic32x4->rstn_gpio, 1);
1000 mdelay(1);
1001 }
1002
1003 snd_soc_component_write(component, AIC32X4_RESET, 0x01);
1004
1005 if (aic32x4->setup)
1006 aic32x4_setup_gpios(component);
1007
1008 clk_set_parent(clocks[0].clk, clocks[1].clk);
1009
1002 /* Power platform configuration */
1003 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
1004 snd_soc_component_write(component, AIC32X4_MICBIAS,
1005 AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V);
1006 }
1007 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
1008 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
1009

--- 266 unchanged lines hidden --- 		1010 /* Power platform configuration */
1011 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
1012 snd_soc_component_write(component, AIC32X4_MICBIAS,
1013 AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V);
1014 }
1015 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
1016 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
1017

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