1 /* 2 * linux/sound/soc/codecs/tlv320aic32x4.c 3 * 4 * Copyright 2011 Vista Silicon S.L. 5 * 6 * Author: Javier Martin <javier.martin@vista-silicon.com> 7 * 8 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 23 * MA 02110-1301, USA. 24 */ 25 26 #include <linux/module.h> 27 #include <linux/moduleparam.h> 28 #include <linux/init.h> 29 #include <linux/delay.h> 30 #include <linux/pm.h> 31 #include <linux/gpio.h> 32 #include <linux/of_gpio.h> 33 #include <linux/cdev.h> 34 #include <linux/slab.h> 35 #include <linux/clk.h> 36 #include <linux/of_clk.h> 37 #include <linux/regulator/consumer.h> 38 39 #include <sound/tlv320aic32x4.h> 40 #include <sound/core.h> 41 #include <sound/pcm.h> 42 #include <sound/pcm_params.h> 43 #include <sound/soc.h> 44 #include <sound/soc-dapm.h> 45 #include <sound/initval.h> 46 #include <sound/tlv.h> 47 48 #include "tlv320aic32x4.h" 49 50 struct aic32x4_rate_divs { 51 u32 mclk; 52 u32 rate; 53 unsigned long pll_rate; 54 u16 dosr; 55 u8 ndac; 56 u8 mdac; 57 u8 aosr; 58 u8 nadc; 59 u8 madc; 60 u8 blck_N; 61 u8 r_block; 62 u8 p_block; 63 }; 64 65 struct aic32x4_priv { 66 struct regmap *regmap; 67 u32 sysclk; 68 u32 power_cfg; 69 u32 micpga_routing; 70 bool swapdacs; 71 int rstn_gpio; 72 struct clk *mclk; 73 const char *mclk_name; 74 75 struct regulator *supply_ldo; 76 struct regulator *supply_iov; 77 struct regulator *supply_dv; 78 struct regulator *supply_av; 79 80 struct aic32x4_setup_data *setup; 81 struct device *dev; 82 }; 83 84 static int mic_bias_event(struct snd_soc_dapm_widget *w, 85 struct snd_kcontrol *kcontrol, int event) 86 { 87 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 88 89 switch (event) { 90 case SND_SOC_DAPM_POST_PMU: 91 /* Change Mic Bias Registor */ 92 snd_soc_component_update_bits(component, AIC32X4_MICBIAS, 93 AIC32x4_MICBIAS_MASK, 94 AIC32X4_MICBIAS_LDOIN | 95 AIC32X4_MICBIAS_2075V); 96 printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__); 97 break; 98 case SND_SOC_DAPM_PRE_PMD: 99 snd_soc_component_update_bits(component, AIC32X4_MICBIAS, 100 AIC32x4_MICBIAS_MASK, 0); 101 printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n", 102 __func__); 103 break; 104 } 105 106 return 0; 107 } 108 109 110 static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol, 111 struct snd_ctl_elem_value *ucontrol) 112 { 113 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 114 u8 val; 115 116 val = snd_soc_component_read32(component, AIC32X4_DINCTL); 117 118 ucontrol->value.integer.value[0] = (val & 0x01); 119 120 return 0; 121 }; 122 123 static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol, 124 struct snd_ctl_elem_value *ucontrol) 125 { 126 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 127 u8 val; 128 u8 gpio_check; 129 130 val = snd_soc_component_read32(component, AIC32X4_DOUTCTL); 131 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 132 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 133 printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n", 134 __func__); 135 return -EINVAL; 136 } 137 138 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH)) 139 return 0; 140 141 if (ucontrol->value.integer.value[0]) 142 val |= ucontrol->value.integer.value[0]; 143 else 144 val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH; 145 146 snd_soc_component_write(component, AIC32X4_DOUTCTL, val); 147 148 return 0; 149 }; 150 151 static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol, 152 struct snd_ctl_elem_value *ucontrol) 153 { 154 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 155 u8 val; 156 157 val = snd_soc_component_read32(component, AIC32X4_SCLKCTL); 158 159 ucontrol->value.integer.value[0] = (val & 0x01); 160 161 return 0; 162 }; 163 164 static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol, 165 struct snd_ctl_elem_value *ucontrol) 166 { 167 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 168 u8 val; 169 u8 gpio_check; 170 171 val = snd_soc_component_read32(component, AIC32X4_MISOCTL); 172 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 173 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 174 printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n", 175 __func__); 176 return -EINVAL; 177 } 178 179 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH)) 180 return 0; 181 182 if (ucontrol->value.integer.value[0]) 183 val |= ucontrol->value.integer.value[0]; 184 else 185 val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH; 186 187 snd_soc_component_write(component, AIC32X4_MISOCTL, val); 188 189 return 0; 190 }; 191 192 static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol, 193 struct snd_ctl_elem_value *ucontrol) 194 { 195 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 196 u8 val; 197 198 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL); 199 ucontrol->value.integer.value[0] = ((val & 0x2) >> 1); 200 201 return 0; 202 }; 203 204 static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol, 205 struct snd_ctl_elem_value *ucontrol) 206 { 207 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 208 u8 val; 209 u8 gpio_check; 210 211 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL); 212 gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT); 213 if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) { 214 printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n", 215 __func__); 216 return -EINVAL; 217 } 218 219 if (ucontrol->value.integer.value[0] == (val & 0x1)) 220 return 0; 221 222 if (ucontrol->value.integer.value[0]) 223 val |= ucontrol->value.integer.value[0]; 224 else 225 val &= 0xfe; 226 227 snd_soc_component_write(component, AIC32X4_GPIOCTL, val); 228 229 return 0; 230 }; 231 232 static const struct snd_kcontrol_new aic32x4_mfp1[] = { 233 SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL), 234 }; 235 236 static const struct snd_kcontrol_new aic32x4_mfp2[] = { 237 SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio), 238 }; 239 240 static const struct snd_kcontrol_new aic32x4_mfp3[] = { 241 SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL), 242 }; 243 244 static const struct snd_kcontrol_new aic32x4_mfp4[] = { 245 SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio), 246 }; 247 248 static const struct snd_kcontrol_new aic32x4_mfp5[] = { 249 SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio, 250 aic32x4_set_mfp5_gpio), 251 }; 252 253 /* 0dB min, 0.5dB steps */ 254 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0); 255 /* -63.5dB min, 0.5dB steps */ 256 static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0); 257 /* -6dB min, 1dB steps */ 258 static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0); 259 /* -12dB min, 0.5dB steps */ 260 static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0); 261 262 static const struct snd_kcontrol_new aic32x4_snd_controls[] = { 263 SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL, 264 AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm), 265 SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN, 266 AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0, 267 tlv_driver_gain), 268 SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN, 269 AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0, 270 tlv_driver_gain), 271 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN, 272 AIC32X4_HPRGAIN, 6, 0x01, 1), 273 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN, 274 AIC32X4_LORGAIN, 6, 0x01, 1), 275 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL, 276 AIC32X4_RMICPGAVOL, 7, 0x01, 1), 277 278 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0), 279 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0), 280 281 SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL, 282 AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol), 283 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL, 284 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5), 285 286 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0), 287 288 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0), 289 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0), 290 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1, 291 4, 0x07, 0), 292 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1, 293 0, 0x03, 0), 294 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2, 295 6, 0x03, 0), 296 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2, 297 1, 0x1F, 0), 298 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3, 299 0, 0x7F, 0), 300 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4, 301 3, 0x1F, 0), 302 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5, 303 3, 0x1F, 0), 304 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6, 305 0, 0x1F, 0), 306 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7, 307 0, 0x0F, 0), 308 }; 309 310 static const struct aic32x4_rate_divs aic32x4_divs[] = { 311 /* 8k rate */ 312 { 12000000, 8000, 57120000, 768, 5, 3, 128, 5, 18, 24, 1, 1 }, 313 { 24000000, 8000, 57120000, 768, 15, 1, 64, 45, 4, 24, 1, 1 }, 314 { 25000000, 8000, 32620000, 768, 15, 1, 64, 45, 4, 24, 1, 1 }, 315 /* 11.025k rate */ 316 { 12000000, 11025, 44217600, 512, 8, 2, 128, 8, 8, 16, 1, 1 }, 317 { 24000000, 11025, 44217600, 512, 16, 1, 64, 32, 4, 16, 1, 1 }, 318 /* 16k rate */ 319 { 12000000, 16000, 57120000, 384, 5, 3, 128, 5, 9, 12, 1, 1 }, 320 { 24000000, 16000, 57120000, 384, 15, 1, 64, 18, 5, 12, 1, 1 }, 321 { 25000000, 16000, 32620000, 384, 15, 1, 64, 18, 5, 12, 1, 1 }, 322 /* 22.05k rate */ 323 { 12000000, 22050, 44217600, 256, 4, 4, 128, 4, 8, 8, 1, 1 }, 324 { 24000000, 22050, 44217600, 256, 16, 1, 64, 16, 4, 8, 1, 1 }, 325 { 25000000, 22050, 19713750, 256, 16, 1, 64, 16, 4, 8, 1, 1 }, 326 /* 32k rate */ 327 { 12000000, 32000, 14112000, 192, 2, 7, 64, 2, 21, 6, 1, 1 }, 328 { 24000000, 32000, 14112000, 192, 7, 2, 64, 7, 6, 6, 1, 1 }, 329 /* 44.1k rate */ 330 { 12000000, 44100, 44217600, 128, 2, 8, 128, 2, 8, 4, 1, 1 }, 331 { 24000000, 44100, 44217600, 128, 8, 2, 64, 8, 4, 4, 1, 1 }, 332 { 25000000, 44100, 19713750, 128, 8, 2, 64, 8, 4, 4, 1, 1 }, 333 /* 48k rate */ 334 { 12000000, 48000, 18432000, 128, 2, 8, 128, 2, 8, 4, 1, 1 }, 335 { 24000000, 48000, 18432000, 128, 8, 2, 64, 8, 4, 4, 1, 1 }, 336 { 25000000, 48000, 75626250, 128, 8, 2, 64, 8, 4, 4, 1, 1 }, 337 338 /* 96k rate */ 339 { 25000000, 96000, 75626250, 64, 4, 4, 64, 4, 4, 1, 1, 9 }, 340 }; 341 342 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = { 343 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0), 344 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0), 345 }; 346 347 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = { 348 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0), 349 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0), 350 }; 351 352 static const struct snd_kcontrol_new lol_output_mixer_controls[] = { 353 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0), 354 }; 355 356 static const struct snd_kcontrol_new lor_output_mixer_controls[] = { 357 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0), 358 }; 359 360 static const char * const resistor_text[] = { 361 "Off", "10 kOhm", "20 kOhm", "40 kOhm", 362 }; 363 364 /* Left mixer pins */ 365 static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text); 366 static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text); 367 static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text); 368 static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text); 369 370 static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text); 371 static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text); 372 static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text); 373 374 static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = { 375 SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum), 376 }; 377 static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = { 378 SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum), 379 }; 380 static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = { 381 SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum), 382 }; 383 static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = { 384 SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum), 385 }; 386 static const struct snd_kcontrol_new cml_to_lmixer_controls[] = { 387 SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum), 388 }; 389 static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = { 390 SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum), 391 }; 392 static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = { 393 SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum), 394 }; 395 396 /* Right mixer pins */ 397 static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text); 398 static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text); 399 static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text); 400 static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text); 401 static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text); 402 static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text); 403 static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text); 404 405 static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = { 406 SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum), 407 }; 408 static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = { 409 SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum), 410 }; 411 static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = { 412 SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum), 413 }; 414 static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = { 415 SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum), 416 }; 417 static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = { 418 SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum), 419 }; 420 static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = { 421 SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum), 422 }; 423 static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = { 424 SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum), 425 }; 426 427 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = { 428 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0), 429 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0, 430 &hpl_output_mixer_controls[0], 431 ARRAY_SIZE(hpl_output_mixer_controls)), 432 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0), 433 434 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0, 435 &lol_output_mixer_controls[0], 436 ARRAY_SIZE(lol_output_mixer_controls)), 437 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0), 438 439 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0), 440 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0, 441 &hpr_output_mixer_controls[0], 442 ARRAY_SIZE(hpr_output_mixer_controls)), 443 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0), 444 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0, 445 &lor_output_mixer_controls[0], 446 ARRAY_SIZE(lor_output_mixer_controls)), 447 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0), 448 449 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0), 450 SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 451 in1r_to_rmixer_controls), 452 SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 453 in2r_to_rmixer_controls), 454 SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 455 in3r_to_rmixer_controls), 456 SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 457 in2l_to_rmixer_controls), 458 SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 459 cmr_to_rmixer_controls), 460 SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 461 in1l_to_rmixer_controls), 462 SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 463 in3l_to_rmixer_controls), 464 465 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0), 466 SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 467 in1l_to_lmixer_controls), 468 SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 469 in2l_to_lmixer_controls), 470 SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 471 in3l_to_lmixer_controls), 472 SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 473 in1r_to_lmixer_controls), 474 SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 475 cml_to_lmixer_controls), 476 SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 477 in2r_to_lmixer_controls), 478 SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 479 in3r_to_lmixer_controls), 480 481 SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event, 482 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 483 484 485 SND_SOC_DAPM_OUTPUT("HPL"), 486 SND_SOC_DAPM_OUTPUT("HPR"), 487 SND_SOC_DAPM_OUTPUT("LOL"), 488 SND_SOC_DAPM_OUTPUT("LOR"), 489 SND_SOC_DAPM_INPUT("IN1_L"), 490 SND_SOC_DAPM_INPUT("IN1_R"), 491 SND_SOC_DAPM_INPUT("IN2_L"), 492 SND_SOC_DAPM_INPUT("IN2_R"), 493 SND_SOC_DAPM_INPUT("IN3_L"), 494 SND_SOC_DAPM_INPUT("IN3_R"), 495 }; 496 497 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = { 498 /* Left Output */ 499 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"}, 500 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"}, 501 502 {"HPL Power", NULL, "HPL Output Mixer"}, 503 {"HPL", NULL, "HPL Power"}, 504 505 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"}, 506 507 {"LOL Power", NULL, "LOL Output Mixer"}, 508 {"LOL", NULL, "LOL Power"}, 509 510 /* Right Output */ 511 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"}, 512 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"}, 513 514 {"HPR Power", NULL, "HPR Output Mixer"}, 515 {"HPR", NULL, "HPR Power"}, 516 517 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"}, 518 519 {"LOR Power", NULL, "LOR Output Mixer"}, 520 {"LOR", NULL, "LOR Power"}, 521 522 /* Right Input */ 523 {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"}, 524 {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 525 {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 526 {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 527 528 {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"}, 529 {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"}, 530 {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"}, 531 {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"}, 532 533 {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"}, 534 {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"}, 535 {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"}, 536 {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"}, 537 538 {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"}, 539 {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 540 {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 541 {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 542 543 {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"}, 544 {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"}, 545 {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"}, 546 {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"}, 547 548 {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"}, 549 {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"}, 550 {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"}, 551 {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"}, 552 553 {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"}, 554 {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"}, 555 {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"}, 556 {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"}, 557 558 /* Left Input */ 559 {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"}, 560 {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"}, 561 {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"}, 562 {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"}, 563 564 {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"}, 565 {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 566 {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 567 {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 568 569 {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"}, 570 {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"}, 571 {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"}, 572 {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"}, 573 574 {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"}, 575 {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 576 {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 577 {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 578 579 {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"}, 580 {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"}, 581 {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"}, 582 {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"}, 583 584 {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"}, 585 {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"}, 586 {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"}, 587 {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"}, 588 589 {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"}, 590 {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"}, 591 {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"}, 592 {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"}, 593 }; 594 595 static const struct regmap_range_cfg aic32x4_regmap_pages[] = { 596 { 597 .selector_reg = 0, 598 .selector_mask = 0xff, 599 .window_start = 0, 600 .window_len = 128, 601 .range_min = 0, 602 .range_max = AIC32X4_RMICPGAVOL, 603 }, 604 }; 605 606 const struct regmap_config aic32x4_regmap_config = { 607 .max_register = AIC32X4_RMICPGAVOL, 608 .ranges = aic32x4_regmap_pages, 609 .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages), 610 }; 611 EXPORT_SYMBOL(aic32x4_regmap_config); 612 613 static inline int aic32x4_get_divs(int mclk, int rate) 614 { 615 int i; 616 617 for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) { 618 if ((aic32x4_divs[i].rate == rate) 619 && (aic32x4_divs[i].mclk == mclk)) { 620 return i; 621 } 622 } 623 printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n"); 624 return -EINVAL; 625 } 626 627 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai, 628 int clk_id, unsigned int freq, int dir) 629 { 630 struct snd_soc_component *component = codec_dai->component; 631 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 632 633 switch (freq) { 634 case 12000000: 635 case 24000000: 636 case 25000000: 637 aic32x4->sysclk = freq; 638 return 0; 639 } 640 printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n"); 641 return -EINVAL; 642 } 643 644 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 645 { 646 struct snd_soc_component *component = codec_dai->component; 647 u8 iface_reg_1 = 0; 648 u8 iface_reg_2 = 0; 649 u8 iface_reg_3 = 0; 650 651 /* set master/slave audio interface */ 652 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 653 case SND_SOC_DAIFMT_CBM_CFM: 654 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER; 655 break; 656 case SND_SOC_DAIFMT_CBS_CFS: 657 break; 658 default: 659 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n"); 660 return -EINVAL; 661 } 662 663 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 664 case SND_SOC_DAIFMT_I2S: 665 break; 666 case SND_SOC_DAIFMT_DSP_A: 667 iface_reg_1 |= (AIC32X4_DSP_MODE << 668 AIC32X4_IFACE1_DATATYPE_SHIFT); 669 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */ 670 iface_reg_2 = 0x01; /* add offset 1 */ 671 break; 672 case SND_SOC_DAIFMT_DSP_B: 673 iface_reg_1 |= (AIC32X4_DSP_MODE << 674 AIC32X4_IFACE1_DATATYPE_SHIFT); 675 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */ 676 break; 677 case SND_SOC_DAIFMT_RIGHT_J: 678 iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE << 679 AIC32X4_IFACE1_DATATYPE_SHIFT); 680 break; 681 case SND_SOC_DAIFMT_LEFT_J: 682 iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE << 683 AIC32X4_IFACE1_DATATYPE_SHIFT); 684 break; 685 default: 686 printk(KERN_ERR "aic32x4: invalid DAI interface format\n"); 687 return -EINVAL; 688 } 689 690 snd_soc_component_update_bits(component, AIC32X4_IFACE1, 691 AIC32X4_IFACE1_DATATYPE_MASK | 692 AIC32X4_IFACE1_MASTER_MASK, iface_reg_1); 693 snd_soc_component_update_bits(component, AIC32X4_IFACE2, 694 AIC32X4_DATA_OFFSET_MASK, iface_reg_2); 695 snd_soc_component_update_bits(component, AIC32X4_IFACE3, 696 AIC32X4_BCLKINV_MASK, iface_reg_3); 697 698 return 0; 699 } 700 701 static int aic32x4_set_processing_blocks(struct snd_soc_component *component, 702 u8 r_block, u8 p_block) 703 { 704 if (r_block > 18 || p_block > 25) 705 return -EINVAL; 706 707 snd_soc_component_write(component, AIC32X4_ADCSPB, r_block); 708 snd_soc_component_write(component, AIC32X4_DACSPB, p_block); 709 710 return 0; 711 } 712 713 static int aic32x4_setup_clocks(struct snd_soc_component *component, 714 unsigned int sample_rate, 715 unsigned int parent_rate) 716 { 717 int i; 718 int ret; 719 720 struct clk_bulk_data clocks[] = { 721 { .id = "pll" }, 722 }; 723 724 i = aic32x4_get_divs(parent_rate, sample_rate); 725 if (i < 0) { 726 printk(KERN_ERR "aic32x4: sampling rate not supported\n"); 727 return i; 728 } 729 730 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 731 if (ret) 732 return ret; 733 734 clk_set_rate(clocks[0].clk, sample_rate); 735 736 aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block); 737 738 /* DAC_MOD_CLK as BDIV_CLKIN */ 739 snd_soc_component_update_bits(component, AIC32X4_IFACE3, 740 AIC32X4_BDIVCLK_MASK, 741 AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT); 742 743 /* NDAC divider value */ 744 snd_soc_component_update_bits(component, AIC32X4_NDAC, 745 AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac); 746 747 /* MDAC divider value */ 748 snd_soc_component_update_bits(component, AIC32X4_MDAC, 749 AIC32X4_MDAC_MASK, aic32x4_divs[i].mdac); 750 751 /* DOSR MSB & LSB values */ 752 snd_soc_component_write(component, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8); 753 snd_soc_component_write(component, AIC32X4_DOSRLSB, (aic32x4_divs[i].dosr & 0xff)); 754 755 /* NADC divider value */ 756 snd_soc_component_update_bits(component, AIC32X4_NADC, 757 AIC32X4_NADC_MASK, aic32x4_divs[i].nadc); 758 759 /* MADC divider value */ 760 snd_soc_component_update_bits(component, AIC32X4_MADC, 761 AIC32X4_MADC_MASK, aic32x4_divs[i].madc); 762 763 /* AOSR value */ 764 snd_soc_component_write(component, AIC32X4_AOSR, aic32x4_divs[i].aosr); 765 766 /* BCLK N divider */ 767 snd_soc_component_update_bits(component, AIC32X4_BCLKN, 768 AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N); 769 770 return 0; 771 } 772 773 static int aic32x4_hw_params(struct snd_pcm_substream *substream, 774 struct snd_pcm_hw_params *params, 775 struct snd_soc_dai *dai) 776 { 777 struct snd_soc_component *component = dai->component; 778 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 779 u8 iface1_reg = 0; 780 u8 dacsetup_reg = 0; 781 782 aic32x4_setup_clocks(component, params_rate(params), aic32x4->sysclk); 783 784 switch (params_width(params)) { 785 case 16: 786 iface1_reg |= (AIC32X4_WORD_LEN_16BITS << 787 AIC32X4_IFACE1_DATALEN_SHIFT); 788 break; 789 case 20: 790 iface1_reg |= (AIC32X4_WORD_LEN_20BITS << 791 AIC32X4_IFACE1_DATALEN_SHIFT); 792 break; 793 case 24: 794 iface1_reg |= (AIC32X4_WORD_LEN_24BITS << 795 AIC32X4_IFACE1_DATALEN_SHIFT); 796 break; 797 case 32: 798 iface1_reg |= (AIC32X4_WORD_LEN_32BITS << 799 AIC32X4_IFACE1_DATALEN_SHIFT); 800 break; 801 } 802 snd_soc_component_update_bits(component, AIC32X4_IFACE1, 803 AIC32X4_IFACE1_DATALEN_MASK, iface1_reg); 804 805 if (params_channels(params) == 1) { 806 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN; 807 } else { 808 if (aic32x4->swapdacs) 809 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN; 810 else 811 dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN; 812 } 813 snd_soc_component_update_bits(component, AIC32X4_DACSETUP, 814 AIC32X4_DAC_CHAN_MASK, dacsetup_reg); 815 816 return 0; 817 } 818 819 static int aic32x4_mute(struct snd_soc_dai *dai, int mute) 820 { 821 struct snd_soc_component *component = dai->component; 822 823 snd_soc_component_update_bits(component, AIC32X4_DACMUTE, 824 AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0); 825 826 return 0; 827 } 828 829 static int aic32x4_set_bias_level(struct snd_soc_component *component, 830 enum snd_soc_bias_level level) 831 { 832 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 833 int ret; 834 835 switch (level) { 836 case SND_SOC_BIAS_ON: 837 /* Switch on master clock */ 838 ret = clk_prepare_enable(aic32x4->mclk); 839 if (ret) { 840 dev_err(component->dev, "Failed to enable master clock\n"); 841 return ret; 842 } 843 844 /* Switch on PLL */ 845 snd_soc_component_update_bits(component, AIC32X4_PLLPR, 846 AIC32X4_PLLEN, AIC32X4_PLLEN); 847 848 /* Switch on NDAC Divider */ 849 snd_soc_component_update_bits(component, AIC32X4_NDAC, 850 AIC32X4_NDACEN, AIC32X4_NDACEN); 851 852 /* Switch on MDAC Divider */ 853 snd_soc_component_update_bits(component, AIC32X4_MDAC, 854 AIC32X4_MDACEN, AIC32X4_MDACEN); 855 856 /* Switch on NADC Divider */ 857 snd_soc_component_update_bits(component, AIC32X4_NADC, 858 AIC32X4_NADCEN, AIC32X4_NADCEN); 859 860 /* Switch on MADC Divider */ 861 snd_soc_component_update_bits(component, AIC32X4_MADC, 862 AIC32X4_MADCEN, AIC32X4_MADCEN); 863 864 /* Switch on BCLK_N Divider */ 865 snd_soc_component_update_bits(component, AIC32X4_BCLKN, 866 AIC32X4_BCLKEN, AIC32X4_BCLKEN); 867 break; 868 case SND_SOC_BIAS_PREPARE: 869 break; 870 case SND_SOC_BIAS_STANDBY: 871 /* Initial cold start */ 872 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) 873 break; 874 875 /* Switch off BCLK_N Divider */ 876 snd_soc_component_update_bits(component, AIC32X4_BCLKN, 877 AIC32X4_BCLKEN, 0); 878 879 /* Switch off MADC Divider */ 880 snd_soc_component_update_bits(component, AIC32X4_MADC, 881 AIC32X4_MADCEN, 0); 882 883 /* Switch off NADC Divider */ 884 snd_soc_component_update_bits(component, AIC32X4_NADC, 885 AIC32X4_NADCEN, 0); 886 887 /* Switch off MDAC Divider */ 888 snd_soc_component_update_bits(component, AIC32X4_MDAC, 889 AIC32X4_MDACEN, 0); 890 891 /* Switch off NDAC Divider */ 892 snd_soc_component_update_bits(component, AIC32X4_NDAC, 893 AIC32X4_NDACEN, 0); 894 895 /* Switch off PLL */ 896 snd_soc_component_update_bits(component, AIC32X4_PLLPR, 897 AIC32X4_PLLEN, 0); 898 899 /* Switch off master clock */ 900 clk_disable_unprepare(aic32x4->mclk); 901 break; 902 case SND_SOC_BIAS_OFF: 903 break; 904 } 905 return 0; 906 } 907 908 #define AIC32X4_RATES SNDRV_PCM_RATE_8000_96000 909 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 910 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 911 912 static const struct snd_soc_dai_ops aic32x4_ops = { 913 .hw_params = aic32x4_hw_params, 914 .digital_mute = aic32x4_mute, 915 .set_fmt = aic32x4_set_dai_fmt, 916 .set_sysclk = aic32x4_set_dai_sysclk, 917 }; 918 919 static struct snd_soc_dai_driver aic32x4_dai = { 920 .name = "tlv320aic32x4-hifi", 921 .playback = { 922 .stream_name = "Playback", 923 .channels_min = 1, 924 .channels_max = 2, 925 .rates = AIC32X4_RATES, 926 .formats = AIC32X4_FORMATS,}, 927 .capture = { 928 .stream_name = "Capture", 929 .channels_min = 1, 930 .channels_max = 2, 931 .rates = AIC32X4_RATES, 932 .formats = AIC32X4_FORMATS,}, 933 .ops = &aic32x4_ops, 934 .symmetric_rates = 1, 935 }; 936 937 static void aic32x4_setup_gpios(struct snd_soc_component *component) 938 { 939 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 940 941 /* setup GPIO functions */ 942 /* MFP1 */ 943 if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) { 944 snd_soc_component_write(component, AIC32X4_DINCTL, 945 aic32x4->setup->gpio_func[0]); 946 snd_soc_add_component_controls(component, aic32x4_mfp1, 947 ARRAY_SIZE(aic32x4_mfp1)); 948 } 949 950 /* MFP2 */ 951 if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) { 952 snd_soc_component_write(component, AIC32X4_DOUTCTL, 953 aic32x4->setup->gpio_func[1]); 954 snd_soc_add_component_controls(component, aic32x4_mfp2, 955 ARRAY_SIZE(aic32x4_mfp2)); 956 } 957 958 /* MFP3 */ 959 if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) { 960 snd_soc_component_write(component, AIC32X4_SCLKCTL, 961 aic32x4->setup->gpio_func[2]); 962 snd_soc_add_component_controls(component, aic32x4_mfp3, 963 ARRAY_SIZE(aic32x4_mfp3)); 964 } 965 966 /* MFP4 */ 967 if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) { 968 snd_soc_component_write(component, AIC32X4_MISOCTL, 969 aic32x4->setup->gpio_func[3]); 970 snd_soc_add_component_controls(component, aic32x4_mfp4, 971 ARRAY_SIZE(aic32x4_mfp4)); 972 } 973 974 /* MFP5 */ 975 if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) { 976 snd_soc_component_write(component, AIC32X4_GPIOCTL, 977 aic32x4->setup->gpio_func[4]); 978 snd_soc_add_component_controls(component, aic32x4_mfp5, 979 ARRAY_SIZE(aic32x4_mfp5)); 980 } 981 } 982 983 static int aic32x4_component_probe(struct snd_soc_component *component) 984 { 985 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 986 u32 tmp_reg; 987 int ret; 988 989 struct clk_bulk_data clocks[] = { 990 { .id = "codec_clkin" }, 991 }; 992 993 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 994 if (ret) 995 return ret; 996 997 if (gpio_is_valid(aic32x4->rstn_gpio)) { 998 ndelay(10); 999 gpio_set_value(aic32x4->rstn_gpio, 1); 1000 mdelay(1); 1001 } 1002 1003 snd_soc_component_write(component, AIC32X4_RESET, 0x01); 1004 1005 if (aic32x4->setup) 1006 aic32x4_setup_gpios(component); 1007 1008 clk_set_parent(clocks[0].clk, clocks[1].clk); 1009 1010 /* Power platform configuration */ 1011 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) { 1012 snd_soc_component_write(component, AIC32X4_MICBIAS, 1013 AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V); 1014 } 1015 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) 1016 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE); 1017 1018 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ? 1019 AIC32X4_LDOCTLEN : 0; 1020 snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg); 1021 1022 tmp_reg = snd_soc_component_read32(component, AIC32X4_CMMODE); 1023 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) 1024 tmp_reg |= AIC32X4_LDOIN_18_36; 1025 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) 1026 tmp_reg |= AIC32X4_LDOIN2HP; 1027 snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg); 1028 1029 /* Mic PGA routing */ 1030 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) 1031 snd_soc_component_write(component, AIC32X4_LMICPGANIN, 1032 AIC32X4_LMICPGANIN_IN2R_10K); 1033 else 1034 snd_soc_component_write(component, AIC32X4_LMICPGANIN, 1035 AIC32X4_LMICPGANIN_CM1L_10K); 1036 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) 1037 snd_soc_component_write(component, AIC32X4_RMICPGANIN, 1038 AIC32X4_RMICPGANIN_IN1L_10K); 1039 else 1040 snd_soc_component_write(component, AIC32X4_RMICPGANIN, 1041 AIC32X4_RMICPGANIN_CM1R_10K); 1042 1043 /* 1044 * Workaround: for an unknown reason, the ADC needs to be powered up 1045 * and down for the first capture to work properly. It seems related to 1046 * a HW BUG or some kind of behavior not documented in the datasheet. 1047 */ 1048 tmp_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP); 1049 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg | 1050 AIC32X4_LADC_EN | AIC32X4_RADC_EN); 1051 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg); 1052 1053 return 0; 1054 } 1055 1056 static const struct snd_soc_component_driver soc_component_dev_aic32x4 = { 1057 .probe = aic32x4_component_probe, 1058 .set_bias_level = aic32x4_set_bias_level, 1059 .controls = aic32x4_snd_controls, 1060 .num_controls = ARRAY_SIZE(aic32x4_snd_controls), 1061 .dapm_widgets = aic32x4_dapm_widgets, 1062 .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets), 1063 .dapm_routes = aic32x4_dapm_routes, 1064 .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes), 1065 .suspend_bias_off = 1, 1066 .idle_bias_on = 1, 1067 .use_pmdown_time = 1, 1068 .endianness = 1, 1069 .non_legacy_dai_naming = 1, 1070 }; 1071 1072 static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4, 1073 struct device_node *np) 1074 { 1075 struct aic32x4_setup_data *aic32x4_setup; 1076 int ret; 1077 1078 aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup), 1079 GFP_KERNEL); 1080 if (!aic32x4_setup) 1081 return -ENOMEM; 1082 1083 ret = of_property_match_string(np, "clock-names", "mclk"); 1084 if (ret < 0) 1085 return -EINVAL; 1086 aic32x4->mclk_name = of_clk_get_parent_name(np, ret); 1087 1088 aic32x4->swapdacs = false; 1089 aic32x4->micpga_routing = 0; 1090 aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0); 1091 1092 if (of_property_read_u32_array(np, "aic32x4-gpio-func", 1093 aic32x4_setup->gpio_func, 5) >= 0) 1094 aic32x4->setup = aic32x4_setup; 1095 return 0; 1096 } 1097 1098 static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4) 1099 { 1100 regulator_disable(aic32x4->supply_iov); 1101 1102 if (!IS_ERR(aic32x4->supply_ldo)) 1103 regulator_disable(aic32x4->supply_ldo); 1104 1105 if (!IS_ERR(aic32x4->supply_dv)) 1106 regulator_disable(aic32x4->supply_dv); 1107 1108 if (!IS_ERR(aic32x4->supply_av)) 1109 regulator_disable(aic32x4->supply_av); 1110 } 1111 1112 static int aic32x4_setup_regulators(struct device *dev, 1113 struct aic32x4_priv *aic32x4) 1114 { 1115 int ret = 0; 1116 1117 aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin"); 1118 aic32x4->supply_iov = devm_regulator_get(dev, "iov"); 1119 aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv"); 1120 aic32x4->supply_av = devm_regulator_get_optional(dev, "av"); 1121 1122 /* Check if the regulator requirements are fulfilled */ 1123 1124 if (IS_ERR(aic32x4->supply_iov)) { 1125 dev_err(dev, "Missing supply 'iov'\n"); 1126 return PTR_ERR(aic32x4->supply_iov); 1127 } 1128 1129 if (IS_ERR(aic32x4->supply_ldo)) { 1130 if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER) 1131 return -EPROBE_DEFER; 1132 1133 if (IS_ERR(aic32x4->supply_dv)) { 1134 dev_err(dev, "Missing supply 'dv' or 'ldoin'\n"); 1135 return PTR_ERR(aic32x4->supply_dv); 1136 } 1137 if (IS_ERR(aic32x4->supply_av)) { 1138 dev_err(dev, "Missing supply 'av' or 'ldoin'\n"); 1139 return PTR_ERR(aic32x4->supply_av); 1140 } 1141 } else { 1142 if (IS_ERR(aic32x4->supply_dv) && 1143 PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER) 1144 return -EPROBE_DEFER; 1145 if (IS_ERR(aic32x4->supply_av) && 1146 PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER) 1147 return -EPROBE_DEFER; 1148 } 1149 1150 ret = regulator_enable(aic32x4->supply_iov); 1151 if (ret) { 1152 dev_err(dev, "Failed to enable regulator iov\n"); 1153 return ret; 1154 } 1155 1156 if (!IS_ERR(aic32x4->supply_ldo)) { 1157 ret = regulator_enable(aic32x4->supply_ldo); 1158 if (ret) { 1159 dev_err(dev, "Failed to enable regulator ldo\n"); 1160 goto error_ldo; 1161 } 1162 } 1163 1164 if (!IS_ERR(aic32x4->supply_dv)) { 1165 ret = regulator_enable(aic32x4->supply_dv); 1166 if (ret) { 1167 dev_err(dev, "Failed to enable regulator dv\n"); 1168 goto error_dv; 1169 } 1170 } 1171 1172 if (!IS_ERR(aic32x4->supply_av)) { 1173 ret = regulator_enable(aic32x4->supply_av); 1174 if (ret) { 1175 dev_err(dev, "Failed to enable regulator av\n"); 1176 goto error_av; 1177 } 1178 } 1179 1180 if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av)) 1181 aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE; 1182 1183 return 0; 1184 1185 error_av: 1186 if (!IS_ERR(aic32x4->supply_dv)) 1187 regulator_disable(aic32x4->supply_dv); 1188 1189 error_dv: 1190 if (!IS_ERR(aic32x4->supply_ldo)) 1191 regulator_disable(aic32x4->supply_ldo); 1192 1193 error_ldo: 1194 regulator_disable(aic32x4->supply_iov); 1195 return ret; 1196 } 1197 1198 int aic32x4_probe(struct device *dev, struct regmap *regmap) 1199 { 1200 struct aic32x4_priv *aic32x4; 1201 struct aic32x4_pdata *pdata = dev->platform_data; 1202 struct device_node *np = dev->of_node; 1203 int ret; 1204 1205 if (IS_ERR(regmap)) 1206 return PTR_ERR(regmap); 1207 1208 aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv), 1209 GFP_KERNEL); 1210 if (aic32x4 == NULL) 1211 return -ENOMEM; 1212 1213 aic32x4->dev = dev; 1214 dev_set_drvdata(dev, aic32x4); 1215 1216 if (pdata) { 1217 aic32x4->power_cfg = pdata->power_cfg; 1218 aic32x4->swapdacs = pdata->swapdacs; 1219 aic32x4->micpga_routing = pdata->micpga_routing; 1220 aic32x4->rstn_gpio = pdata->rstn_gpio; 1221 aic32x4->mclk_name = "mclk"; 1222 } else if (np) { 1223 ret = aic32x4_parse_dt(aic32x4, np); 1224 if (ret) { 1225 dev_err(dev, "Failed to parse DT node\n"); 1226 return ret; 1227 } 1228 } else { 1229 aic32x4->power_cfg = 0; 1230 aic32x4->swapdacs = false; 1231 aic32x4->micpga_routing = 0; 1232 aic32x4->rstn_gpio = -1; 1233 aic32x4->mclk_name = "mclk"; 1234 } 1235 1236 aic32x4->mclk = devm_clk_get(dev, "mclk"); 1237 if (IS_ERR(aic32x4->mclk)) { 1238 dev_err(dev, "Failed getting the mclk. The current implementation does not support the usage of this codec without mclk\n"); 1239 return PTR_ERR(aic32x4->mclk); 1240 } 1241 1242 ret = aic32x4_register_clocks(dev, aic32x4->mclk_name); 1243 if (ret) 1244 return ret; 1245 1246 if (gpio_is_valid(aic32x4->rstn_gpio)) { 1247 ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio, 1248 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn"); 1249 if (ret != 0) 1250 return ret; 1251 } 1252 1253 ret = aic32x4_setup_regulators(dev, aic32x4); 1254 if (ret) { 1255 dev_err(dev, "Failed to setup regulators\n"); 1256 return ret; 1257 } 1258 1259 ret = devm_snd_soc_register_component(dev, 1260 &soc_component_dev_aic32x4, &aic32x4_dai, 1); 1261 if (ret) { 1262 dev_err(dev, "Failed to register component\n"); 1263 aic32x4_disable_regulators(aic32x4); 1264 return ret; 1265 } 1266 1267 return 0; 1268 } 1269 EXPORT_SYMBOL(aic32x4_probe); 1270 1271 int aic32x4_remove(struct device *dev) 1272 { 1273 struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev); 1274 1275 aic32x4_disable_regulators(aic32x4); 1276 1277 return 0; 1278 } 1279 EXPORT_SYMBOL(aic32x4_remove); 1280 1281 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver"); 1282 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>"); 1283 MODULE_LICENSE("GPL"); 1284