| cs35l45.h (fa8c052b4c614aa1d2d60e5c9f40e9d885bf9511) | cs35l45.h (6085f9e6dc1973cf98ee7f5dcf629939e50f1b84) |
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| 1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2/* 3 * cs35l45.h - CS35L45 ALSA SoC audio driver 4 * 5 * Copyright 2019-2022 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * --- 37 unchanged lines hidden (view full) --- 46#define CS35L45_ASPTX1_INPUT 0x00004C20 47#define CS35L45_ASPTX2_INPUT 0x00004C24 48#define CS35L45_ASPTX3_INPUT 0x00004C28 49#define CS35L45_ASPTX4_INPUT 0x00004C2C 50#define CS35L45_ASPTX5_INPUT 0x00004C30 51#define CS35L45_LDPM_CONFIG 0x00006404 52#define CS35L45_AMP_PCM_CONTROL 0x00007000 53#define CS35L45_AMP_PCM_HPF_TST 0x00007004 | 1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2/* 3 * cs35l45.h - CS35L45 ALSA SoC audio driver 4 * 5 * Copyright 2019-2022 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * --- 37 unchanged lines hidden (view full) --- 46#define CS35L45_ASPTX1_INPUT 0x00004C20 47#define CS35L45_ASPTX2_INPUT 0x00004C24 48#define CS35L45_ASPTX3_INPUT 0x00004C28 49#define CS35L45_ASPTX4_INPUT 0x00004C2C 50#define CS35L45_ASPTX5_INPUT 0x00004C30 51#define CS35L45_LDPM_CONFIG 0x00006404 52#define CS35L45_AMP_PCM_CONTROL 0x00007000 53#define CS35L45_AMP_PCM_HPF_TST 0x00007004 |
| 54#define CS35L45_IRQ1_CFG 0x0000E000 55#define CS35L45_IRQ1_STATUS 0x0000E004 56#define CS35L45_IRQ1_EINT_1 0x0000E010 57#define CS35L45_IRQ1_EINT_2 0x0000E014 58#define CS35L45_IRQ1_EINT_3 0x0000E018 |
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| 54#define CS35L45_IRQ1_EINT_4 0x0000E01C | 59#define CS35L45_IRQ1_EINT_4 0x0000E01C |
| 60#define CS35L45_IRQ1_EINT_5 0x0000E020 61#define CS35L45_IRQ1_EINT_7 0x0000E028 62#define CS35L45_IRQ1_EINT_8 0x0000E02C 63#define CS35L45_IRQ1_EINT_18 0x0000E054 64#define CS35L45_IRQ1_STS_1 0x0000E090 65#define CS35L45_IRQ1_STS_2 0x0000E094 66#define CS35L45_IRQ1_STS_3 0x0000E098 67#define CS35L45_IRQ1_STS_4 0x0000E09C 68#define CS35L45_IRQ1_STS_5 0x0000E0A0 69#define CS35L45_IRQ1_STS_7 0x0000E0A8 70#define CS35L45_IRQ1_STS_8 0x0000E0AC 71#define CS35L45_IRQ1_STS_18 0x0000E0D4 72#define CS35L45_IRQ1_MASK_1 0x0000E110 73#define CS35L45_IRQ1_MASK_2 0x0000E114 74#define CS35L45_IRQ1_MASK_3 0x0000E118 75#define CS35L45_IRQ1_MASK_4 0x0000E11C 76#define CS35L45_IRQ1_MASK_5 0x0000E120 77#define CS35L45_IRQ1_MASK_6 0x0000E124 78#define CS35L45_IRQ1_MASK_7 0x0000E128 79#define CS35L45_IRQ1_MASK_8 0x0000E12C 80#define CS35L45_IRQ1_MASK_9 0x0000E130 81#define CS35L45_IRQ1_MASK_10 0x0000E134 82#define CS35L45_IRQ1_MASK_11 0x0000E138 83#define CS35L45_IRQ1_MASK_12 0x0000E13C 84#define CS35L45_IRQ1_MASK_13 0x0000E140 85#define CS35L45_IRQ1_MASK_14 0x0000E144 86#define CS35L45_IRQ1_MASK_15 0x0000E148 87#define CS35L45_IRQ1_MASK_16 0x0000E14C 88#define CS35L45_IRQ1_MASK_17 0x0000E150 89#define CS35L45_IRQ1_MASK_18 0x0000E154 |
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| 55#define CS35L45_GPIO_STATUS1 0x0000F000 56#define CS35L45_GPIO1_CTRL1 0x0000F008 57#define CS35L45_GPIO2_CTRL1 0x0000F00C 58#define CS35L45_GPIO3_CTRL1 0x0000F010 59#define CS35L45_LASTREG 0x0000F010 60/* SFT_RESET */ 61#define CS35L45_SOFT_RESET_TRIGGER 0x5A000000 62 --- 120 unchanged lines hidden (view full) --- 183#define CS35L45_GPIO_POL_MASK BIT(12) 184 185/* SYNC_GPIO1, INTB_GPIO2_MCLK_REF, GPIO3 */ 186#define CS35L45_GPIO_CTRL_SHIFT 20 187#define CS35L45_GPIO_CTRL_MASK GENMASK(22, 20) 188#define CS35L45_GPIO_INVERT_SHIFT 19 189#define CS35L45_GPIO_INVERT_MASK BIT(19) 190 | 90#define CS35L45_GPIO_STATUS1 0x0000F000 91#define CS35L45_GPIO1_CTRL1 0x0000F008 92#define CS35L45_GPIO2_CTRL1 0x0000F00C 93#define CS35L45_GPIO3_CTRL1 0x0000F010 94#define CS35L45_LASTREG 0x0000F010 95/* SFT_RESET */ 96#define CS35L45_SOFT_RESET_TRIGGER 0x5A000000 97 --- 120 unchanged lines hidden (view full) --- 218#define CS35L45_GPIO_POL_MASK BIT(12) 219 220/* SYNC_GPIO1, INTB_GPIO2_MCLK_REF, GPIO3 */ 221#define CS35L45_GPIO_CTRL_SHIFT 20 222#define CS35L45_GPIO_CTRL_MASK GENMASK(22, 20) 223#define CS35L45_GPIO_INVERT_SHIFT 19 224#define CS35L45_GPIO_INVERT_MASK BIT(19) 225 |
| 226/* CS35L45_IRQ1_EINT_1 */ 227#define CS35L45_BST_UVP_ERR_SHIFT 7 228#define CS35L45_BST_UVP_ERR_MASK BIT(7) 229#define CS35L45_BST_SHORT_ERR_SHIFT 8 230#define CS35L45_BST_SHORT_ERR_MASK BIT(8) 231#define CS35L45_TEMP_ERR_SHIFT 17 232#define CS35L45_TEMP_ERR_MASK BIT(17) 233#define CS35L45_MSM_GLOBAL_EN_ASSERT_SHIFT 22 234#define CS35L45_MSM_GLOBAL_EN_ASSERT_MASK BIT(22) 235#define CS35L45_UVLO_VDDBATT_ERR_SHIFT 29 236#define CS35L45_UVLO_VDDBATT_ERR_MASK BIT(29) 237#define CS35L45_AMP_SHORT_ERR_SHIFT 31 238#define CS35L45_AMP_SHORT_ERR_MASK BIT(31) 239 240/* CS35L45_IRQ1_EINT_2 */ 241#define CS35L45_DSP_WDT_EXPIRE_SHIFT 4 242#define CS35L45_DSP_WDT_EXPIRE_MASK BIT(4) 243 244/* CS35L45_IRQ1_EINT_3 */ 245#define CS35L45_PLL_LOCK_FLAG_SHIFT 1 246#define CS35L45_PLL_LOCK_FLAG_MASK BIT(1) 247#define CS35L45_PLL_UNLOCK_FLAG_RISE_SHIFT 4 248#define CS35L45_PLL_UNLOCK_FLAG_RISE_MASK BIT(4) 249#define CS35L45_AMP_CAL_ERR_SHIFT 25 250#define CS35L45_AMP_CAL_ERR_MASK BIT(25) 251 252/* CS35L45_IRQ1_EINT_18 */ 253#define CS35L45_GLOBAL_ERROR_SHIFT 15 254#define CS35L45_GLOBAL_ERROR_MASK BIT(15) 255#define CS35L45_UVLO_VDDLV_ERR_SHIFT 16 256#define CS35L45_UVLO_VDDLV_ERR_MASK BIT(16) 257 |
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| 191/* Mixer sources */ 192#define CS35L45_PCM_SRC_MASK 0x7F 193#define CS35L45_PCM_SRC_ZERO 0x00 194#define CS35L45_PCM_SRC_ASP_RX1 0x08 195#define CS35L45_PCM_SRC_ASP_RX2 0x09 196#define CS35L45_PCM_SRC_VMON 0x18 197#define CS35L45_PCM_SRC_IMON 0x19 198#define CS35L45_PCM_SRC_ERR_VOL 0x20 --- 13 unchanged lines hidden (view full) --- 212 SNDRV_PCM_FMTBIT_S24_3LE| \ 213 SNDRV_PCM_FMTBIT_S24_LE) 214 215#define CS35L45_RATES (SNDRV_PCM_RATE_44100 | \ 216 SNDRV_PCM_RATE_48000 | \ 217 SNDRV_PCM_RATE_88200 | \ 218 SNDRV_PCM_RATE_96000) 219 | 258/* Mixer sources */ 259#define CS35L45_PCM_SRC_MASK 0x7F 260#define CS35L45_PCM_SRC_ZERO 0x00 261#define CS35L45_PCM_SRC_ASP_RX1 0x08 262#define CS35L45_PCM_SRC_ASP_RX2 0x09 263#define CS35L45_PCM_SRC_VMON 0x18 264#define CS35L45_PCM_SRC_IMON 0x19 265#define CS35L45_PCM_SRC_ERR_VOL 0x20 --- 13 unchanged lines hidden (view full) --- 279 SNDRV_PCM_FMTBIT_S24_3LE| \ 280 SNDRV_PCM_FMTBIT_S24_LE) 281 282#define CS35L45_RATES (SNDRV_PCM_RATE_44100 | \ 283 SNDRV_PCM_RATE_48000 | \ 284 SNDRV_PCM_RATE_88200 | \ 285 SNDRV_PCM_RATE_96000) 286 |
| 287/* 288 * IRQs 289 */ 290#define CS35L45_IRQ(_irq, _name, _hand) \ 291 { \ 292 .irq = CS35L45_ ## _irq ## _IRQ,\ 293 .name = _name, \ 294 .handler = _hand, \ 295 } 296 297struct cs35l45_irq { 298 int irq; 299 const char *name; 300 irqreturn_t (*handler)(int irq, void *data); 301}; 302 303#define CS35L45_REG_IRQ(_reg, _irq) \ 304 [CS35L45_ ## _irq ## _IRQ] = { \ 305 .reg_offset = (CS35L45_ ## _reg) - CS35L45_IRQ1_EINT_1, \ 306 .mask = CS35L45_ ## _irq ## _MASK \ 307 } 308 309enum cs35l45_irq_list { 310 CS35L45_AMP_SHORT_ERR_IRQ, 311 CS35L45_UVLO_VDDBATT_ERR_IRQ, 312 CS35L45_BST_SHORT_ERR_IRQ, 313 CS35L45_BST_UVP_ERR_IRQ, 314 CS35L45_TEMP_ERR_IRQ, 315 CS35L45_AMP_CAL_ERR_IRQ, 316 CS35L45_UVLO_VDDLV_ERR_IRQ, 317 CS35L45_GLOBAL_ERROR_IRQ, 318 CS35L45_DSP_WDT_EXPIRE_IRQ, 319 CS35L45_PLL_UNLOCK_FLAG_RISE_IRQ, 320 CS35L45_PLL_LOCK_FLAG_IRQ, 321 CS35L45_NUM_IRQ 322}; 323 |
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| 220struct cs35l45_private { 221 struct device *dev; 222 struct regmap *regmap; 223 struct gpio_desc *reset_gpio; 224 struct regulator *vdd_batt; 225 struct regulator *vdd_a; 226 bool initialized; 227 bool sysclk_set; 228 u8 slot_width; 229 u8 slot_count; | 324struct cs35l45_private { 325 struct device *dev; 326 struct regmap *regmap; 327 struct gpio_desc *reset_gpio; 328 struct regulator *vdd_batt; 329 struct regulator *vdd_a; 330 bool initialized; 331 bool sysclk_set; 332 u8 slot_width; 333 u8 slot_count; |
| 334 int irq_invert; 335 int irq; 336 struct regmap_irq_chip_data *irq_data; |
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| 230}; 231 232extern const struct dev_pm_ops cs35l45_pm_ops; 233extern const struct regmap_config cs35l45_i2c_regmap; 234extern const struct regmap_config cs35l45_spi_regmap; 235int cs35l45_apply_patch(struct cs35l45_private *cs35l45); 236unsigned int cs35l45_get_clk_freq_id(unsigned int freq); 237int cs35l45_probe(struct cs35l45_private *cs35l45); 238void cs35l45_remove(struct cs35l45_private *cs35l45); 239 240#endif /* CS35L45_H */ | 337}; 338 339extern const struct dev_pm_ops cs35l45_pm_ops; 340extern const struct regmap_config cs35l45_i2c_regmap; 341extern const struct regmap_config cs35l45_spi_regmap; 342int cs35l45_apply_patch(struct cs35l45_private *cs35l45); 343unsigned int cs35l45_get_clk_freq_id(unsigned int freq); 344int cs35l45_probe(struct cs35l45_private *cs35l45); 345void cs35l45_remove(struct cs35l45_private *cs35l45); 346 347#endif /* CS35L45_H */ |